Dual self-aligned gate endcap (SAGE) architectures

An integrated circuit structure, comprising:

• a first three-dimensional semiconductor body having a cut along a length of the first three-dimensional semiconductor body;
• a second three-dimensional semiconductor body parallel with the first three-dimensional semiconductor body;
• a first gate endcap isolation structure between the first three-dimensional semiconductor body and the second three-dimensional semiconductor body;
• and
• a second gate endcap isolation structure in a location of the cut along the length of the first three-dimensional semiconductor body, wherein the second gate endcap isolation structure has a bottom surface above a bottom surface of the first gate endcap isolation structure, and wherein the second gate endcap isolation structure is spaced apart from and is not in contact with the first three-dimensional semiconductor body.

An integrated circuit structure, comprising:

• a first three-dimensional semiconductor body having a cut along a length of the first three-dimensional semiconductor body;
• a second three-dimensional semiconductor body parallel with the first three-dimensional semiconductor body;
• a first gate endcap isolation structure between the first three-dimensional semiconductor body and the second three-dimensional semiconductor body;
• and
• a second gate endcap isolation structure in a location of the cut along the length of the first three-dimensional semiconductor body, wherein the second gate endcap isolation structure is spaced apart from and is not in contact with the first three-dimensional semiconductor body;
• and
• a third three-dimensional semiconductor body parallel with the first and second three-dimensional semiconductor bodies, the third three-dimensional semiconductor body spaced apart from the second gate endcap isolation structure by a first spacing at a side of the second gate endcap isolation structure opposite the first gate endcap isolation structure, wherein the second three-dimensional semiconductor body is spaced apart from the first gate endcap isolation structure by a second spacing less than the first spacing, and wherein the first and second gate endcap isolation structures have an uppermost surface at least as high as an uppermost surface of the first, second and third three-dimensional bodies.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first three-dimensional semiconductor body having a cut along a length of the first three-dimensional semiconductor body;
• a second three-dimensional semiconductor body parallel with the first three-dimensional semiconductor body;
• a first gate endcap isolation structure between the first three-dimensional semiconductor body and the second three-dimensional semiconductor body;
• and
• a second gate endcap isolation structure in a location of the cut along the length of the first three-dimensional semiconductor body, the second endcap isolation structure parallel with and discrete from the first endcap isolation structure without an intervening three-dimensional semiconductor body between the first and second endcap isolation structures, wherein the second gate endcap isolation structure is spaced apart from and is not in contact with the first three-dimensional semiconductor body, and wherein the first and second gate endcap isolation structures have an uppermost surface at least as high as an uppermost surface of the first and second three-dimensional bodies.