Semiconductor device with reduced flicker noise

A semiconductor device, comprising:

• source/drain regions disposed in a semiconductor substrate, wherein the source/drain regions are laterally spaced;
• a gate stack disposed over the semiconductor substrate and between the source/drain regions;
• sidewall spacers disposed over the semiconductor substrate and along a first sidewall of the gate stack and a second sidewall of the gate stack opposite the first sidewall of the gate stack;
• a cap layer disposed over the gate stack and the semiconductor substrate, wherein the cap layer extends along the sidewall spacers toward the semiconductor substrate on opposite sides of the gate stack, wherein the cap layer comprises a first sidewall disposed on a first side of the gate stack and a second sidewall disposed on the first side of the gate stack, the first sidewall and the second sidewall facing away from the gate stack, and wherein the first sidewall of the cap layer is spaced a first distance from the first sidewall of the gate stack and the second sidewall of the cap layer is spaced from the first sidewall of the gate stack by a second distance that is less than the first distance;
• and
• a dielectric layer disposed over the cap layer, wherein the dielectric layer extends laterally beyond the first sidewall of the cap layer.

A semiconductor device, comprising:

• a pair of source/drain regions disposed in a semiconductor substrate, wherein the source/drain regions are laterally spaced;
• a gate stack disposed over the semiconductor substrate and disposed between the source/drain regions;
• a cap layer disposed over the gate stack, wherein the cap layer extends along opposite sides of the gate stack toward an upper surface of the semiconductor substrate;
• a dielectric layer disposed over the cap layer, wherein the dielectric layer extends laterally beyond sidewalls of the cap layer;
• and
• an isolation structure disposed in the semiconductor substrate, wherein the source/drain regions are disposed between the isolation structure and the gate stack, and wherein the cap layer comprises a lateral extension segment that extends laterally over the upper surface of the semiconductor substrate to at least partially cover the isolation structure.