Transistor layout to reduce kink effect
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
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Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.
Claims20
An integrated chip, comprising:
- an isolation structure arranged within a substrate and having one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate;
- and
- a conductive gate arranged over the substrate between a source region and a drain region, wherein the conductive gate extends into the one or more trenches disposed along the opposing sides of the active region of the substrate, and wherein the conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.
An integrated chip, comprising:
- an isolation structure arranged within a substrate and surrounding an active region of the substrate, wherein the isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure;
- a source region and a drain region disposed within the substrate and surrounded by the isolation structure;
- and
- a conductive gate structure arranged over the substrate between the source region and the drain region, wherein the conductive gate structure extends into the one or more trenches, and wherein the conductive gate structure has an upper surface that is both above the uppermost surface of the isolation structure and extends to be directly over the isolation structure on opposing sides of the active region.
An integrated chip, comprising:
- an isolation structure arranged within a substrate and having one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an upper surface of the substrate;
- a conductive gate layer arranged vertically over the upper surface of the substrate between a source region and a drain region;
- wherein a first segment of the one or more trenches extends in a first direction and a second segment of the one or more trenches extends in a second direction that is perpendicular to the first direction;
- and
- wherein the conductive gate layer is disposed within the first segment and the second segment.
Dependencies are inferred from the claim text.