Deep source and drain for transistor structures with back-side contact metallization

A transistor structure, comprising:

• a fin comprising a channel region over a sub-channel region, the channel region comprising a first semiconductor material having a first impurity concentration;
• a gate electrode adjacent to a sidewall of the channel region, and over a dielectric material that is adjacent to a sidewall of the sub-channel region;
• a source region and a drain region on opposite sides of the gate electrode, wherein at least one of the source region and the drain region comprises:
• a second semiconductor material that has a second impurity concentration greater than the first impurity concentration;
• and
• a third semiconductor material between the second semiconductor material and the sidewall of both the channel region and the sub-channel region, the third semiconductor material having a third impurity concentration exceeding the first impurity concentration, but less than the second impurity concentration;
• first contact metallization coupled to a first side of the source region or drain region, the first contact metallization in contact with the second semiconductor material;
• and
• second contact metallization coupled to a second side of the source region or drain region, opposite the first side, the second contact metallization also in contact with the second semiconductor material, wherein:
• the first semiconductor material is monocrystalline and comprises predominantly silicon;
• the second semiconductor material is in contact with the third semiconductor material;
• and
• the second and third semiconductor materials have crystallinity that is epitaxial with that of the first semiconductor material.

An integrated circuit (IC), comprising:

• a plurality of first interconnect metallization levels;
• a plurality of second interconnect metallization levels;
• and
• an active device layer between the first and second interconnect metallization levels, the active device layer comprising a plurality of transistor structures, wherein at least one of the transistor structures further comprises:
• a fin comprising a channel region over a sub-channel region, the channel region comprising a first semiconductor material having a first impurity concentration;
• a gate electrode adjacent to a sidewall of the channel region, and over a dielectric material that is adjacent to a sidewall of the sub-channel region;
• a source region and a drain region on opposite sides of the gate electrode, wherein at least one of the source region and the drain region comprises:
• a second semiconductor material that has a second impurity concentration greater than the first impurity concentration;
• and
• a third semiconductor material in contact with the sidewall of both the channel region and the sub-channel region, the third semiconductor material having a third impurity concentration exceeding the first impurity concentration, but less than the second impurity concentration, wherein the third semiconductor material is between the second semiconductor material and the sidewall of both the channel region and the sub-channel region;
• wherein the first interconnect metallization levels comprise first contact metallization coupled to a first side of the source region or drain region, the first contact metallization in contact with the second semiconductor material;
• and
• wherein the second interconnect metallization levels comprise second contact metallization coupled to a second side of the source region or drain region, opposite the first side, the second contact metallization extending through a portion of the third semiconductor material and in contact with the second semiconductor material.