Semiconductor memory device and method for manufacturing the same

A semiconductor memory device comprising:

• a substrate having an active pattern including a first source/drain region and a second source/drain region;
• a gate electrode intersecting the active pattern and extending in a first direction;
• a line structure intersecting the active pattern and extending in a second direction crossing the first direction, the line structure comprising a bit line electrically connected to the first source/drain region;
• a spacer disposed on a sidewall of the line structure;
• a metal contact electrically connected to the second source/drain region, the metal contact spaced apart from the bit line with the spacer interposed therebetween;
• an interface layer disposed between the second source/drain region and the metal contact;
• and
• a data storage element disposed on the metal contact,
• wherein the interface layer includes graphene.

A semiconductor memory device comprising:

• a substrate having an active pattern, the active pattern, which has a long axis in a first direction, including a first source/drain region and a pair of second source/drain regions spaced apart from each other in the first direction with the first source/drain region interposed therebetween;
• a device isolation layer filling a first trench which is provided in the substrate to define the active pattern;
• a pair of gate electrodes intersecting the active pattern and extending in a second direction crossing the first direction, each of the pair of gate electrodes provided in a second trench between the first and second source/drain regions and having a top surface lower than a top surface of the active pattern;
• a gate dielectric layer disposed between the active pattern and each of the pair of gate electrodes;
• a gate capping layer provided on each of the pair of gate electrodes to fill the second trench;
• an insulating layer disposed on the substrate;
• a line structure intersecting the active pattern on the insulating layer and extending in a third direction crossing the first and second directions, the line structure comprising:
• a conductive pattern penetrating the insulating layer so as to be connected to the first source/drain region;
• a bit line disposed on the conductive pattern;
• and
• a barrier pattern disposed between the bit line and the conductive pattern;
• a pair of spacers provided on both sidewalls of the line structure, respectively;
• a pair of metal contacts electrically connected to the pair of second source/drain regions, respectively, being in contact with the pair of spacers, respectively, and spaced apart from the line structure by the pair of spacers;
• a pair of interface layers disposed between the pair of second source/drain regions and the pair of metal contacts, respectively;
• first electrodes disposed on the pair of metal contacts, respectively;
• a second electrode on the first electrodes;
• and
• a dielectric layer disposed between the second electrode and the first electrodes,
• wherein each of the pair of second source/drain regions has a recessed top surface lower than a top surface of the substrate,
• wherein each of the pair of interface layers covers the recessed top surface,
• wherein each of the pair of interface layers includes graphene, and
• wherein each of the pair of interface layers forms an ohmic contact between each of the pair of second source/drain regions and each of the pair of metal contacts, respectively.