Semiconductor device including three-dimensional field-effect transistor with curved multi-layered source/drain pattern

A semiconductor device, comprising

• a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction;
• a first channel pattern on the first active pattern, the first channel pattern including semiconductor patterns, which are vertically stacked;
• a first source/drain pattern in a recess of an upper portion of the first active pattern;
• a gate electrode on the first active pattern and extending in a second direction crossing the first direction;
• and
• a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns,
• wherein:
• the first source/drain pattern includes a buffer layer covering inner sides of the recess, a main layer on the buffer layer to fill the recess, and an intermediate layer between the buffer layer and the main layer,
• the gate spacer includes a first spacer sidewall facing in the first direction, and a second spacer sidewall, which is an inner sidewall of the opening, when viewed in a plan view,
• the buffer layer covers the second spacer sidewall, and
• the second spacer sidewall is spaced apart from the main layer.

A semiconductor device, comprising

• a substrate including a first active region and a second active region;
• a first active pattern on the first active region of the substrate and extending in a first direction;
• a first source/drain pattern in a first recess of an upper portion of the first active pattern;
• a second active pattern on the second active region of the substrate and extending in the first direction;
• a second source/drain pattern in a second recess of an upper portion of the second active pattern;
• a gate electrode on a first channel pattern of the upper portion of the first active pattern and a second channel pattern of the upper portion of the second active pattern and extending in a second direction crossing the first direction, each of the first and second channel patterns including semiconductor patterns, which are vertically stacked, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns,
• a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns;
• active contacts connected to the first source/drain pattern and the second source/drain pattern;
• a plurality of interconnection lines connected to the active contacts;
• a plurality of vias provided below the interconnection lines;
• and
• interlayer insulating layers covering the active contacts, the interconnection lines, and the vias,
• wherein:
• the first source/drain pattern includes a buffer layer covering inner sides of the first recess, an intermediate layer on the buffer layer, and a main layer on the intermediate layer to fill a remaining space of the first recess,
• when viewed in a plan view, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and
• the outer side surface and the inner side surface are curved surfaces that are convexly curved toward the gate electrode closest to the buffer layer.