Integrated circuit structure with source/drain spacers

A device, comprising:

• a semiconductor substrate;
• a first dielectric feature on the semiconductor substrate and having a first sidewall surface;
• a fourth second dielectric feature on the semiconductor substrate and having a fourth second sidewall surface, the first sidewall surface facing the second sidewall surface;
• a stack of channel layers extending between the first sidewall surface and the second sidewall surface;
• a gate structure engaging with the stack of channel layers and extending along a first direction;
• a gate spacer on sidewalls of the gate structure, wherein a portion of the gate spacer extends between the first sidewall surface and the second sidewall surface;
• and
• a source/drain feature over the semiconductor substrate having a bottom portion extending between the first sidewall surface and the second sidewall surface and a top portion over the first and second dielectric features.

A device, comprising:

• a semiconductor substrate having a substrate surface;
• a stack of channel layers on the semiconductor substrate;
• a gate structure engaging with the stack of channel layers and extending along a first direction;
• a gate spacer on sidewalls of the gate structure;
• a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, the first sidewall surfaces extending in parallel to the first direction;
• and
• a first dielectric feature on second sidewall surfaces of the stack of channel layers, the second sidewall surfaces extending perpendicular to the first direction,
• wherein the source/drain feature has a top width along the first direction greater than a bottom width along the first direction, and
• wherein the source/drain feature directly contacts a top surface and a sidewall of the first dielectric feature.