Semiconductor device structure and method for forming the same

A semiconductor device structure, comprising:

• first nanostructures formed over a substrate;
• a first gate structure wrapped around the first nanostructures;
• a first inner spacer formed beside the first gate structure between the first nanostructures;
• a first source/drain epitaxial structure formed beside the first nanostructures;
• second nanostructures formed over the first nanostructures;
• a second gate structure wrapped around the second nanostructures;
• a second inner spacer formed beside the second gate structure between the second nanostructures;
• a second source/drain epitaxial structure formed beside the second nanostructures;
• and
• a power rail electrically connected to the first source/drain epitaxial structure, wherein a top surface of the power rail is lower than a bottommost surface of the first nanostructures,
• wherein a width of the first inner spacer is greater than a width of the second inner spacer, and a thickness of the first nanostructures is greater than a thickness of the second nanostructures.

A method for forming a semiconductor device structure, comprising:

• forming a first semiconductor stack with first semiconductor layers and second semiconductor layers alternately stacked over a substrate;
• forming a second semiconductor stack with third semiconductor layers and fourth semiconductor layers alternately stacked over the first semiconductor stack;
• laterally etching the first semiconductor layers to form first openings exposing sidewalls of the first semiconductor layers;
• laterally etching the third semiconductor layers to form second openings exposing sidewalls of the third semiconductor layers;
• forming first inner spacers in the first opening;
• forming second inner spacers in the second opening;
• removing the first semiconductor layers and the third semiconductor layers;
• forming a first gate structure wrapped around the second semiconductor layers;
• forming a second gate structure wrapped around the fourth semiconductor layers over the first gate structure,
• wherein a Ge concentration of the second semiconductor layers is higher than a Ge concentration of the fourth semiconductor layers, and a Ge concentration of the first semiconductor layers is higher than a Ge concentration of the third semiconductor layers.