US 11,688,765 B2Granted

Semiconductor device and method for manufacturing the same

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorYuhki Fujino

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Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.

Claims7

Dependent claims

A semiconductor device comprising:

a first electrode;
a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region;
a third semiconductor region of the first conductivity type provided on another part of the first semiconductor region, the third semiconductor region including
a first region separated from the second semiconductor region in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region, and
a second region provided between the first region and the second semiconductor region, an impurity concentration of the first conductivity type in the second region being higher than an impurity concentration of the first conductivity type in the first region;
a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;
a fifth semiconductor region of the first conductivity type provided on a part of the fourth semiconductor region;
a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region;
and
a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region wherein,
an impurity concentration of the second conductivity type in the second semiconductor region is higher than an impurity concentration of the first conductivity type in the third semiconductor region, and
a length of the third semiconductor region in the second direction is longer than a length of the second semiconductor region in the second direction.

10 more elements

A semiconductor device comprising:

a first electrode;
a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;
a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region;
a third semiconductor region of the first conductivity type provided on another part of the first semiconductor region, the third semiconductor region including
a first region separated from the second semiconductor region in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region, and
a second region provided between the first region and the second semiconductor region, an impurity concentration of the first conductivity type in the second region being higher than an impurity concentration of the first conductivity type in the first region;
a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;
a fifth semiconductor region of the first conductivity type provided on a part of the fourth semiconductor region;
an intermediate region of a first conductivity type provided between the first semiconductor region and the second semiconductor region, and between the first semiconductor region and the third semiconductor region, an impurity concentration of the first conductivity type in the intermediate region being lower than an impurity concentration of the first conductivity type in the first semiconductor region, the intermediate region including
a first portion provided between the first semiconductor region and the second semiconductor region, and between the first semiconductor region and the second region, and
a second portion provided between the first semiconductor region and the first region, an impurity concentration of the first conductivity type in the second portion being lower than an impurity concentration of the first conductivity type in the first portion;
a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region;
and
a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region.

11 more elements

A semiconductor device comprising:

a first electrode;
a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;
an intermediate region, an impurity concentration of the first conductivity type in the intermediate region being lower than an impurity concentration of the first conductivity type in the first semiconductor region,
the intermediate region including:
a first portion provided on a part of the first semiconductor region;
and
a second portion provided on another part of the first semiconductor region, an impurity concentration of the first conductivity type in the second portion being lower than an impurity concentration of the first conductivity type in the first portion;
a second semiconductor region of a second conductivity type provided on a part of the first portion;
an insulating part, the second semiconductor region being provided around the insulating part in a second direction that is perpendicular to a first direction directed from the first electrode to the first semiconductor region;
a third semiconductor region of the first conductivity type provided on another part of the first portion and the second portion;
a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;
a fifth semiconductor region of the first conductivity type provided on the fourth semiconductor region;
a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region;
and
a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/198,334Filed 11 Mar 2021
Priority: JP JP2020-15323311 Sep 2020
Published: US 2022/0085159 A117 Mar 2022
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 30/66
Double-diffused metal-oxide semiconductor [DMOS] FETs: vertical dmos [vdmos] fets
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors