US 11,688,757 B2Granted

Semiconductor device, manufacturing method, imaging element, and electronic device

AssigneeSony Semiconductor Solutions Corporation

InventorHidenobu Tsugawa

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Abstract

The present disclosure relates to a semiconductor device, a manufacturing method, an imaging element, and an electronic device capable of reducing manufacturing steps in a stacked structure obtained by stacking two or more semiconductor substrates. The semiconductor device has a stacked structure obtained by stacking at least a first semiconductor substrate in which a first wiring layer is stacked on a first semiconductor layer and a second semiconductor substrate in which a second wiring layer is stacked on a second semiconductor layer. Then, a through via which electrically connects the first semiconductor substrate and the second semiconductor substrate to each other and penetrates at least the first semiconductor layer is formed in an embedded oxide film formed when element isolation of a semiconductor element formed in the first semiconductor layer is performed. The present technology is applicable to, for example, a stacked semiconductor device.

Claims18

Dependent claims

A semiconductor device, comprising:

a first structure in which a first wiring layer is stacked on a first layer that includes a first semiconductor layer so that a surface of the first wiring layer contacts a surface of the first semiconductor layer;
a second structure in which a second wiring layer is stacked on a second semiconductor layer so that a surface of the second wiring layer contacts a surface of the second semiconductor layer, wherein the first layer is joined to the second wiring layer at a joining surface between the first layer and the second wiring layer;
a through via disposed in the first wiring layer and that penetrates through the surface of the first wiring layer and the surface of the first layer to the joining surface to electrically connect the first structure and the second structure to each other, wherein the through via penetrates through an insulating film of the first layer, wherein at least part of the insulating film of the first layer isolates a source and a drain of a transistor disposed in the first semiconductor layer from surrounding semiconductor material of the first semiconductor layer, wherein the joining surface is planar, and wherein, in a cross sectional view of a region that covers the transistor and the through via in a plan view, the joining surface over the region includes a combination of a surface of the insulating film of the first layer in contact with a surface of an insulating film of the second wiring layer and a surface of a wire in the second wiring layer in contact with the insulating film of the first layer and the through via;
a first wiring disposed in the first wiring layer and extending in a first direction in the plan view, the first wiring being electrically connected to the source;
a second wiring disposed in the first wiring layer and separate from the first wiring, the second wiring extending in the first direction and being electrically connected to the drain;
and
a third wiring disposed in the first wiring layer and separate from the first wiring and the second wiring, the third wiring extending in the first direction and being electrically connected to the through via.

4 more elements

An imaging element, comprising:

a sensor structure in which a first wiring layer is stacked on a first layer that includes a first semiconductor layer so that a surface of the first wiring layer contacts a surface of the first semiconductor layer;
a logic structure in which a second wiring layer is stacked on a second semiconductor layer so that a surface of the second wiring layer contacts a surface of the second semiconductor layer, wherein the first layer is joined to the second wiring layer at a joining surface between the first layer and the second wiring layer;
a through via disposed in the first wiring layer and that penetrates through the surface of the first wiring layer and the surface of the first layer to the joining surface to electrically connect the first structure and the second structure to each other, wherein the through via penetrates through an insulating film of the first layer, wherein at least part of the insulating film of the first layer isolates a source and a drain of a transistor disposed in the first semiconductor layer from surrounding semiconductor material of the first semiconductor layer, wherein the joining surface is planar, and wherein, in a cross sectional view of a region that covers the transistor and the through via in a plan view, the joining surface over the region includes a combination of a surface of the insulating film of the first layer in contact with a surface of an insulating film of the second wiring layer and a surface of a wire in the second wiring layer in contact with the insulating film of the first layer and the through via;
a first wiring disposed in the first wiring layer and extending in a first direction in the plan view, the first wiring being electrically connected to the source;
a second wiring disposed in the first wiring layer and separate from the first wiring, the second wiring extending in the first direction and being electrically connected to the drain;
and
a third wiring disposed in the first wiring layer and separate from the first wiring and the second wiring, the third wiring extending in the first direction and being electrically connected to the through via.

4 more elements

An electronic device, comprising:

a signal processing circuit;
and
an imaging element, including:
sensor structure in which a first wiring layer is stacked on a first layer that includes a first semiconductor layer so that a surface of the first wiring layer contacts a surface of the first semiconductor layer;
a logic structure in which a second wiring layer is stacked on a second semiconductor layer so that a surface of the second wiring layer contacts a surface of the second semiconductor layer, wherein the first layer is joined to the second wiring layer at a joining surface between the first layer and the second wiring layer;
a through via disposed in the first wiring layer and that penetrates through the surface of the first wiring layer and the surface of the first layer to the joining surface to electrically connect the first structure and the second structure to each other, wherein the through via penetrates through an insulating film of the first layer, wherein at least part of the insulating film of the first layer isolates a source and a drain of a transistor disposed in the first semiconductor layer from surrounding semiconductor material of the first semiconductor layer, wherein the joining surface is planar, and wherein, in a cross sectional view of a region that covers the transistor and the through via in a plan view, the joining surface over the region includes a combination of a surface of the insulating film of the first layer in contact with a surface of an insulating film of the second wiring layer and a surface of a wire in the second wiring layer in contact with the insulating film of the first layer and the through via;
a first wiring disposed in the first wiring layer and extending in a first direction in the plan view, the first wiring being electrically connected to the source;
a second wiring disposed in the first wiring layer and separate from the first wiring, the second wiring extending in the first direction and being electrically connected to the drain;
and
a third wiring disposed in the first wiring layer and separate from the first wiring and the second wiring, the third wiring extending in the first direction and being electrically connected to the through via.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/496,006Filed 13 Apr 2018
Priority: JP 2017-08959928 Apr 2017
Published: US 2021/0118937 A122 Apr 2021
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H10F 39/014
Manufacture or treatment of image sensors covered by group H10F39/12: of CMOS image sensors
H10F 39/018
Manufacture or treatment of image sensors covered by group H10F39/12: of hybrid image sensors
H10F 39/199
Image sensors: back-illuminated image sensors
H10F 39/8037
Pixels having integrated switching, control, storage or amplification elements: the integrated elements comprising a transistor