3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
Estimating the term…
Abstract
A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.
Claims20
A device, comprising:
- an integrated circuit package;
- and
- a plurality of partitions of integrated circuits enclosed within the integrated circuit package,
- each of the partitions having:
- memory cells configured to store parameters representative of a set of artificial neurons;
- and
- logic circuit configured to receive input data of the artificial neurons and generate output data of the artificial neurons responding to the input data.
A system, comprising:
- a bus;
- and
- a plurality of partitions of integrated circuits enclosed within an integrated circuit package, each of the partitions having:
- memory cells configured to store parameters representative of a set of artificial neurons;
- and
- logic circuit configured to receive input data of the artificial neurons and generate output data of the artificial neurons responding to the input data.
An integrated circuit comprising:
- a plurality of partitions enclosed within the intergrated circuit, each of the partitions having:
- memory cells configured to store parameters of a set of artificial neurons;
- and
- logic circuit configured to receive data of the artificial neurons and generate output data of the artificial neurons.
Dependencies are inferred from the claim text.