Integrated circuit device and method

An integrated circuit (IC) device, comprising:

• a first active region of a first semiconductor type;
• a second active region of a second semiconductor type, the second semiconductor type different from the first semiconductor type;
• a plurality of gate regions extending over and across the first and second active regions;
• a plurality of contact structures over and in electrical contact with corresponding portions of the first and second active regions;
• and
• a conductive layer over the plurality of gate regions and the plurality of contact structures, the conductive layer comprising:
• a first conductive pattern electrically coupling a first set of the contact structures over the first active region together,
• a second conductive pattern electrically coupling a second set of the contact structures over the first active region together,
• a third conductive pattern electrically coupling the plurality of gate regions together, and
• a fourth conductive pattern electrically coupling the contact structures over the second active region together.

A method, comprising:

• forming, over a substrate, a first active region of a first semiconductor type and a second active region of a second semiconductor type different from the first semiconductor type, the first and second active regions extending along a first axis;
• forming a gate structure over the first and second active regions, the gate structure extending continuously from the first active region to the second active region along a second axis transverse to the first axis, wherein
• the gate structure and the first active region are configured as a first transistor of a first type, and
• the gate structure and the second active region are configured as a second transistor of a second type different from the first type;
• and
• depositing a conductive layer over the gate structure and the first and second active regions, and patterning the conductive layer into a plurality of conductive patterns extending along the first axis, the plurality of conductive patterns comprising
• a first conductive pattern electrically coupled to a first terminal of the first transistor,
• a second conductive pattern electrically coupled to a second terminal of the first transistor,
• a third conductive pattern electrically coupled to the first terminal of the first transistor, and
• a fourth conductive pattern electrically coupled to first and second terminals of the second transistor to form the second transistor as a dummy transistor.