US 11,688,730 B2Granted

Method and system of manufacturing conductors and semiconductor device which includes conductors

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsKam-Tou Sio, Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young

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Abstract

A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Claims20

Dependent claims

A system for manufacturing a semiconductor device, the system comprising:

at least one processor;
and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating fin shapes, long axes of the fin shapes extending substantially parallel to a first direction;
generating first and second conductor shapes correspondingly over the fin shapes, long axes of the first and second conductor shapes extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction;
arranging a first sequence of alternating ones of the first and second conductor shapes relative to the first direction;
inserting a corresponding one of the second conductor shapes between each neighboring pair of corresponding ones of the first conductor shapes;
generating first, second, and third cap shapes correspondingly over the first and second conductor shapes, long axes of the first, second, and third cap shapes extending substantially parallel to the second direction;
generating first cut patterns over selected portions of corresponding ones of the first cap shapes and over corresponding portions of corresponding neighboring ones of the third cap shapes;
designating the first cut patterns as selective for a first etch sensitivity corresponding to the first cap shapes;
generating second cut patterns over selected portions of corresponding ones of the second cap shapes and over corresponding portions of corresponding neighboring ones of the third cap shapes;
and
designating the second cut patterns as selective for a second etch sensitivity corresponding to the second cap shapes.

12 more elements

A system for manufacturing a semiconductor device, the system comprising:

at least one processor;
and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating a base shape including parallel transistor-channel structure shapes arranged in a first direction;
generating first conductor shapes arranged parallel to a second direction and which are capped with corresponding first or second caps, each first cap having a first etch sensitivity, each second cap having a second etch sensitivity, the second direction being orthogonal to the first direction;
and
generating second conductor shapes arranged parallel to and interspersed with the first conductor shapes and which are capped with third caps, each third cap having a third etch sensitivity;
and
wherein:
the first conductor shapes are organized into at least first and second sets;
and
the first, second and third etch sensitivities are different from each other.

11 more elements

A system for manufacturing a semiconductor device, the system comprising:

at least one processor;
and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the generating the layout diagram including:
generating parallel transistor-channel structure shapes arranged in a first direction;
generating first conductor shapes arranged parallel to a second direction wherein the second direction is orthogonal to the first direction and wherein the first conductor shapes include:
a first set of the first conductor shapes which are each capped with a first cap having a first etch sensitivity;
a second set of the first conductor shapes which are each capped with a second cap having a second etch sensitivity;
second conductor shapes arranged parallel to and interspersed with the first conductor shapes and which are capped with third caps, each third cap having a third etch sensitivity;
and
wherein the first, second and third etch sensitivities are different from each other.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/225,664Filed 8 Apr 2021 · division
Priority: 29 Nov 2016
Published: US 2021/0225831 A122 Jul 2021
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes

Family

Application62/427,570Us provisional application · filed 29 Nov 2016
Application15/676,225Parent of this division · filed 14 Aug 2017
Application16/544,373Parent of this division · filed 19 Aug 2019
US 10,388,644 B2Parent of this division · filed 20 Aug 2019
US 2021/0225831 A1Pre-grant publication · published 22 Jul 2021
US 10,978,439 B2Parent of this division
US 2018/0151552 A1Published application
US 2019/0371784 A1Published application
US 11,688,730 B2This patent

From the US filing history. Foreign family members aren’t listed.