Chip package structure and manufacturing method thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsXinRu Zeng, Peng Chen, Houde Zhou
Life of this patent
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Abstract
A chip package structure includes a chip stack and a redistribution layer. The chip stack includes multiple chips stacked together, a molding layer encapsulating the multiple chips, and a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The redistribution layer is above the molding layer and includes a conductive layer coupled to the vertical conductive element, and an insulating layer over and partially exposing the conductive layer.
Claims20
A chip package structure, comprising:
- a chip stack comprising:
- multiple chips stacked together, each of the multiple chips comprising a bonding pad not covered by the multiple chips;
- a molding layer encapsulating the multiple chips, wherein a first subset of the multiple chips is separated from a second subset of the multiple chips by the molding layer;
- a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad;
- and
- a redistribution layer above the molding layer and having:
- a conductive layer coupled to the vertical conductive element;
- and
- an insulating layer over and partially exposing the conductive layer.
A chip package structure, comprising:
- a chip stack comprising:
- multiple chips stacked together, wherein each of the multiple chips comprises multiple vertically-orientated strings of memory cells and a bonding pad;
- a molding layer encapsulating the multiple chips, wherein a first subset of the multiple chips is separated from a second subset of the multiple chips by the molding layer;
- and
- a vertical conductive element penetrating through the molding layer, wherein the vertical conductive element is disposed on and electrically connected to the bonding pad;
- and
- a redistribution layer disposed on the chip stack and electrically connected to the vertical conductive element.
Dependencies are inferred from the claim text.