Semiconductor device assembly with embossed solder mask having non-planar features and associated methods and systems

A method, comprising:

• attaching a first surface of a solder mask to a package substrate including conductive bumps, the solder mask including a second surface opposite the first surface and openings in which the conductive bumps are located;
• forming a first plurality of non-planar surface features on a first region of the second surface of the solder mask;
• forming a second plurality of non-planar surface features on a second region of the second surface of the solder mask, wherein the second region is laterally spaced farther away from any of the openings than the first region such that the second region is more susceptible to delamination than the first region, and wherein the second plurality of non-planar features has a greater average depth than does the first plurality of non-planar features such that an adhesion strength of the fill material at the second plurality of non-planar features is greater than an adhesion strength of the fill material at the first plurality of non-planar features;
• attaching a semiconductor die to the package substrate such that conductive pillars coupled to bond pads of the semiconductor die electrically couple the semiconductor die with the conductive bumps of the package substrate;
• and
• filling at least a portion of a space between the package substrate and the semiconductor die with a fill material such that the fill material contacts the first and second pluralities of non-planar surface features on the second surface of the solder mask.

A semiconductor assembly, comprising:

• a package substrate including conductive bumps;
• a solder mask including a first surface attached to the package substrate, a second surface opposite the first surface, the second surface having a first region with a first uneven surface profile, a second region with a second uneven surface profile with a larger average feature depth than does the first uneven surface profile of the first region, and openings extending between the first and second surfaces in which the conductive bumps are placed, wherein the second region is laterally spaced farther away from any of the openings than the first region such that the second region is more susceptible to delamination than the first region,
• wherein the larger average feature depth of the second uneven surface profile is effective to produce a greater adhesion strength of the fill material at the second uneven surface profile than an adhesion strength of the fill material at the first uneven surface;
• a semiconductor die including bond pads, to which conductive pillars are electrically coupled, wherein individual conductive pillars are coupled to corresponding conductive bumps;
• and
• a fill material in a space between the package substrate and the semiconductor die, wherein a portion of the fill material at least partially fills the first uneven surface profile and the second uneven surface profile of the second surface.