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US 11,688,691 B2Granted
Method of making standard cells having via rail and deep via structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
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Abstract
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
Claims20
A method for forming a semiconductor structure, comprising:
- forming a plurality of source/drain (S/D) contact structures;
- depositing a first conductive material to form first and second via rail structures, wherein at least one of the first and second via rail structures is in physical contact with two or more S/D contact structures of the plurality of S/D contact structures, wherein the at least one of the first and second via rail structures extends above opposing vertical sidewalls of each of the two or more S/D contact structures of the plurality of S/D contact structures;
- depositing a second conductive material to form a deep via in physical contact with the second via rail structure;
- forming a first interconnect line above the first and second via rail structures and in physical contact with the first via rail structure, wherein the first interconnect line is formed in a lowest wiring level;
- and
- forming a second interconnect line over and physically connected to the deep via, wherein the second interconnect line is in a second lowest wiring level.
3 more elements
A method for forming a semiconductor structure, comprising:
- forming a plurality of source/drain (S/D) contact structures;
- depositing a first dielectric layer over the plurality of S/D contact structures;
- forming a first via rail in the first dielectric layer, wherein the first via rail is physically connected to a top surface of a S/D contact structure of the plurality of S/D contact structures, wherein the first via rail extends above opposing sides of the S/D contact structure, wherein the opposing sides of the S/D contact structure are connected to the top surface of the S/D contact structure;
- forming a second via rail in the first dielectric layer;
- depositing a second dielectric layer over the first dielectric layer;
- forming a first interconnect line in the second dielectric layer and in physical contact with the first via rail, wherein the first interconnect line is formed in a lowest wiring level;
- depositing a third dielectric layer over the second dielectric layer;
- etching the second and third dielectric layers to form an opening, wherein the opening exposes a portion of the second via rail;
- depositing a conductive material in the opening to form a deep via, wherein a bottom portion of the deep via is in physical contact with the exposed portion of the second via rail;
- and
- forming a second interconnect line in the third dielectric layer—and in contact with a top portion of the deep via, wherein the second interconnect line is formed in a second lowest wiring level.
8 more elements
A method for forming a semiconductor structure, comprising:
- forming a plurality of transistor devices, comprising first and second pluralities of source/drain (S/D) contact structures;
- depositing a dielectric layer on the first and second pluralities of S/D contact structures;
- etching the dielectric layer to expose the first and second pluralities of S/D contact structures, respectively;
- depositing a conductive material on top surfaces of first and second pluralities of S/D contact structures to form first and second via rails, respectively, wherein:
- the first via rail extends above opposing sides of each of the first plurality of S/D contact structures, wherein the opposing sides of each of the first plurality of S/D contact structures are perpendicular to the top surfaces;
- and
- the second via rail extends above opposing sides of each of the second plurality of S/D contact structures wherein the opposing sides of each of the second plurality of S/D contact structures are perpendicular to the top surfaces;
- forming a first interconnect line physically connected to the first via rail, wherein the first interconnect line is formed in a lowest wiring level;
- forming a deep via in physical contact with the second via rail at a bottom portion of the deep via;
- and
- forming a second interconnect line in physical contact with the deep via at a top portion of the deep via, wherein the second interconnect line is formed in a second lowest wiring level.
8 more elements
Dependencies are inferred from the claim text.