Semiconductor device including an input/output circuit

A semiconductor device comprising:

• a substrate having a first area and a second area surrounded by the first area;
• a plurality of input/output areas in the first area,
• the plurality of input/output areas arranged in a first direction parallel to an upper surface of the substrate and in a second direction different from the first direction,
• each of the plurality of input/output areas including semiconductor elements providing an input/output circuit, lower wiring patterns connected to the semiconductor elements, an input/output pin connected to the lower wiring patterns, and upper wiring patterns,
• such that the plurality of input/output areas have input/output pins;
• a core region in the second area;
• and
• a plurality of bumps connected to the input/output pins by the upper wiring patterns at a same height as the input/output pins, wherein
• the lower wiring patterns provide an input/output wiring pattern connecting the input/output circuit to the core region, and
• the plurality of input/output areas include a first input/output area and a second input/output area,
• a distance between the input/output wiring pattern and the input/output pin in the first input/output area is a first distance,
• a distance between the input/output wiring pattern and the input/output pin in the second input/output area is a second distance, and
• the second distance is different from the first distance.

A semiconductor device comprising:

• a substrate;
• a plurality of input/output areas in a first area of the substrate;
• a core region connected to the plurality of input/output areas, the core region being configured to receive an input signal from the plurality of input/output areas or to transmit an output signal to the plurality of input/output areas;
• and
• a plurality of bumps electrically connected to the input/output areas,
• wherein each of the plurality of input/output areas includes a logic circuit area, a protection circuit area, and writing patterns connecting one of the plurality of bumps to the protection circuit area,
• the logic circuit area includes an input/output wiring pattern connected to the core region,
• the protection circuit area is connected to at least one of the plurality of bumps,
• the writing patterns are different from the input/output wiring pattern, and
• in at least one of the plurality of input/output areas, at least one of the wiring patterns traverses a boundary between the logic circuit area and the protection circuit area.