MIM capacitor structures

A method of manufacturing an integrated circuit structure, the method comprising:

• forming a lower level back end of line (BEOL) wiring layer including lower level metal lines and an upper level BEOL wiring layer including upper level metal lines, the lower level metal lines connected to the upper level metal lines by an interconnect, the lower and upper level metal lines extending in a first direction in a plan view and defining a fill shape area therebetween in the plan view that does not include elements of the upper or lower level BEOL wiring layers;
• and
• forming a metal-insulator-metal (MIM) capacitor in the first fill shape area that extends in a thickness direction of the integrated circuit structure at least partially from the lower level BEOL layer to the upper level BEOL layer and does not overlap in the plan view with the lower level metal lines or upper level metal lines,
• wherein a first electrode of the MIM capacitor is formed at a same level in the thickness direction as the lower level metal lines, and all remaining portions of the MIM capacitor are formed between the lower level metal lines and the upper level metal lines in the thickness direction.