Semiconductor package and method for fabricating a semiconductor package
AssigneeInfineon Technologies Austria AG
InventorsRalf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Abstract
A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
Claims16
A method for fabricating a semiconductor package, the method comprising:
- providing a SiC semiconductor wafer comprising a plurality of power transistor circuits;
- depositing a first metal layer on the SiC semiconductor wafer;
- singulating the SiC semiconductor wafer into individual power semiconductor chips, each power semiconductor chip comprising at least one power transistor circuit;
- providing a leadframe part comprising Cu;
- arranging at least one of the power semiconductor chips on the leadframe part such that the first metal layer faces the leadframe part;
- and
- diffusion soldering the at least one power semiconductor chip to the leadframe part such that the first metal layer and the leadframe part form at least one intermetallic phase,
- wherein a first main side of the at least one power semiconductor chip is completely covered by the first metal layer.
A method for fabricating a semiconductor package, the method comprising:
- providing a SiC semiconductor wafer comprising a plurality of power transistor circuits;
- depositing a first metal layer on the SiC semiconductor wafer;
- singulating the SiC semiconductor wafer into individual power semiconductor chips, each power semiconductor chip comprising at least one power transistor circuit;
- providing a leadframe part comprising Cu;
- arranging at least one of the power semiconductor chips on the leadframe part such that the first metal layer faces the leadframe part;
- arranging at least one additional metal or metal alloy layer between the power semiconductor chip and the first metal layer;
- and
- diffusion soldering the at least one power semiconductor chip to the leadframe part such that the first metal layer and the leadframe part form at least one intermetallic phase.
A method for fabricating a semiconductor package, the method comprising:
- providing a SiC semiconductor wafer comprising a plurality of power transistor circuits;
- depositing a first metal layer on the SiC semiconductor wafer;
- singulating the SiC semiconductor wafer into individual power semiconductor chips, each power semiconductor chip comprising at least one power transistor circuit;
- providing a leadframe part comprising Cu;
- arranging at least one of the power semiconductor chips on the leadframe part such that the first metal layer faces the leadframe part;
- and
- diffusion soldering the at least one power semiconductor chip to the leadframe part such that the first metal layer and the leadframe part form at least one intermetallic phase,
- wherein each power semiconductor chip comprises a vertical transistor structure having a first power electrode arranged on a first main side of the SiC semiconductor wafer and a second power electrode arranged on a second main side of the SiC semiconductor wafer opposite the first main side,
- wherein the first metal layer covers the first main side of the SiC semiconductor wafer, and
- wherein the first power electrode is electrically and mechanically coupled to the leadframe part by an intermetallic compound formed by the diffusion soldering.
Dependencies are inferred from the claim text.