Test line structure, semiconductor structure and method for forming test line structure

A semiconductor structure, comprising:

• a semiconductor substrate;
• a first test line structure, comprising:
• a plurality of first diagnosis units over the semiconductor substrate, each comprising:
• a first interconnect structure having a first routing pattern;
• and
• a plurality of first micro pad units, each configured to connect the first interconnect structures of two adjacent first diagnosis units of the first diagnosis units;
• and
• a second test line structure, comprising:
• a plurality of second diagnosis units over the first diagnosis units, each comprising:
• a second interconnect structure having a second routing pattern;
• and
• a plurality of second micro pad units, each configured to connect the second interconnect structures of two adjacent second diagnosis units of the second diagnosis units,
• wherein the first routing patterns of the first interconnect structures in the first diagnosis units are different, and the second routing patterns of the second interconnect structures in the second diagnosis units are different.

A semiconductor structure, comprising:

• a semiconductor substrate;
• a plurality of diagnosis units over the semiconductor substrate, each comprising:
• a first interconnect structure having a first routing pattern;
• and
• a second interconnect structure having a second routing pattern corresponding to the first routing pattern;
• a plurality of first micro pad units;
• and
• a plurality of second micro pad units,
• wherein the first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and the second interconnect structures of the diagnosis units are connected in series to form a second test chain through the second micro pad units,
• wherein in each of the diagnosis units, the first interconnect structure is separated from the second interconnect structure.