Reduced source/drain coupling for CFET
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Alexander Reznicek, Chanro Park, Chun-Chen Yeh
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Abstract
A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.
Claims19
A complementary field effect transistor (CFET) device comprising:
- an nFET channel device and a pFET channel device;
- and
- an airgap defined directly between the nFET channel device and the pFET channel device such that a width of the airgap is approximately equal to a width of the nFET channel device.
A complementary field effect transistor (CFET) device comprising:
- an nFET channel device;
- a pFET channel device vertically aligned with the nFET channel device;
- and
- an airgap defined directly between the nFET channel device and the pFET channel device.
Dependencies are inferred from the claim text.