Semiconductor structure with air gap and method sealing the air gap

A semiconductor structure, comprising:

• a substrate having an active region and an isolation region;
• gate stacks on the substrate that extend over the active region and the isolation region;
• a gate spacer on sidewalls of the gate stacks;
• an interlevel dielectric (ILD) layer over the substrate, the ILD layer having a top surface and a bottom surface, the top surface having a width greater than a width of the bottom surface;
• and
• an air gap between a sidewall of the ILD layer and the gate spacer,
• wherein the air gap is confined within the isolation region without extending into the active region.

A method of fabricating a semiconductor structure, comprising:

• receiving a substrate having an active region and an isolation region;
• forming gate stacks on the substrate that extend from the active region to the isolation region;
• forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks;
• forming an interlevel dielectric (ILD) layer over the substrate;
• forming an etch stop layer surrounding the ILD layer;
• forming a mask layer over the substrate that exposes a first portion of the outer gate spacer and a portion of the ILD layer;
• removing the exposed first portion of the outer gate spacer without removing a second portion of the outer gate spacer, wherein the removal results in an air gap between the inner gate spacer and the etch stop layer;
• and
• performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.