Retention voltage management for a volatile memory
AssigneeApple Inc.
InventorsShahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
Life of this patent
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Abstract
An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
Claims20
An apparatus, comprising:
- a memory circuit including a plurality of sub-arrays, wherein the memory circuit is configured to implement a retention mode according to stored information indicating voltage sensitivities for the plurality of sub-arrays;
- and
- a voltage control circuit coupled to a power supply node, wherein during the retention mode for the plurality of sub-arrays, the voltage control circuit is configured to:
- generate, based on the stored information, a first retention voltage level for a first subset of the plurality of sub-arrays;
- and
- generate, based on the stored information, a second retention voltage level, higher than the first retention voltage level, for a second subset of the plurality of sub-arrays;
- and
- wherein the first and second retention voltage levels are lower than a power supply voltage level of the power supply node, and wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the first retention voltage level.
A method comprising:
- coupling, by a voltage control circuit, a power supply node to a plurality of sub-arrays included in a memory circuit;
- during activation of a retention mode for the memory circuit:
- de-coupling, by the voltage control circuit, the plurality of sub-arrays from the power supply node;
- generating, by the voltage control circuit using stored information, a first retention voltage level for a first subset of the plurality of sub-arrays;
- and
- generating, by the voltage control circuit using the stored information, a second retention voltage level, higher than the first retention voltage level, for a second subset of the plurality of sub-arrays;
- and
- wherein the first and second retention voltage levels are lower than a power supply voltage level of the power supply node, and wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the first retention voltage level.
A memory circuit, comprising:
- a plurality of sub-arrays, including respective pluralities of data storage cells, configured to retain data values when a retention mode is active;
- a voltage control circuit configured to:
- couple the plurality of sub-arrays to a power supply node;
- during activation of the retention mode:
- decouple the plurality of sub-arrays from the power supply node;
- using stored information, generate a first retention supply signal for a first subset of the plurality of sub-arrays, wherein a voltage level of the first retention supply signal is less than a voltage level on the power supply node;
- and
- using the stored information, generate a second retention supply signal for a second subset of the plurality of sub-arrays, wherein a voltage level of the second retention supply signal is greater than the voltage level of the first retention supply signal and less than the voltage level on the power supply node;
- and
- wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the voltage level of the first retention supply signal.
Dependencies are inferred from the claim text.