Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates
AssigneeMicron Technology, Inc.
InventorsTingjun Xie, Zhengang Chen
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Abstract
A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- determining a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of a plurality of write-to-read delay times for the memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of the plurality of write-to-read delay times, wherein the first set comprises different write-to-read delay times than the second set;
- determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion;
- and
- responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the range of the plurality of write-to-read delay times.
A method of operation of a memory sub-system comprising:
- determining a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of a plurality of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of the plurality of write-to-read delay times, wherein the first set comprises different write-to-read delay times than the second set;
- determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion;
- and
- responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the range of the plurality of write-to-read delay times.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- determining a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of a plurality of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of the plurality of write-to-read delay times, wherein the first set comprises different write-to-read delay times than the second set;
- determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion;
- and
- responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the range of the plurality of write-to-read delay times.
Dependencies are inferred from the claim text.