Debugging memory devices
AssigneeMicron Technology, Inc.
InventorJunam Kim
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.
Claims25
A method, comprising:
- receiving, via a first signal path, a first signal from a first memory device comprising a plurality of memory cells of a first type;
- interrupting, at a controller performing a set of processes associated with memory access commands for a second memory device comprising a plurality of memory cells of a second type, one or more of the set of processes, wherein interrupting the one or more of the set of processes is based at least in part on receiving the first signal;
- and
- receiving, via a second signal path and based at least in part on interrupting the one or more of the set of processes, a second signal from the first memory device, wherein the second signal indicates one of a plurality of types of errors associated with the first memory device and the second signal.
A method, comprising:
- receiving an output of a first logic gate, wherein the output of the first logic gate indicates whether a first error has occurred at a first memory device comprising a first plurality of memory cells of a first type, a second error has occurred at a second memory device comprising a second plurality of memory cells of the first type, or both;
- interrupting one or more processes associated with memory access commands for a third memory device comprising a first plurality of memory cells of a second type, wherein interrupting the one or more processes is based at least in part on receiving the output of the first logic gate;
- and
- receiving an output of a second logic gate, wherein the output of the second logic gate indicates one or more of a plurality of types of errors associated with the first memory device, the second memory device, or both.
A system, comprising:
- a first subsystem having a first memory interface, the first subsystem comprising a plurality of memory cells of a first type and coupled with a first signal path;
- and
- a second subsystem having a second memory interface, the second subsystem coupled with the first signal path, wherein the second subsystem comprises a plurality of memory cells of a second type and is configured to write data associated with one or more errors associated with the first subsystem to the plurality of memory cells of the second type based at least in part on receiving signaling via the first signal path.
Dependencies are inferred from the claim text.