Digital circuit testing and analysis module, system and method thereof

A digital circuit testing and analyzing system comprising a plurality of digital circuit testing and analysis modules configured to be embedded in a digital integrated circuit connected in a cascade coupling, each digital circuit testing and analysis module including:

• a memory configured to have 2D×one-bit wide memory locations;
• and
• at least three digital signal input busses including a first digital signal input bus, a second digital signal input bus and a third digital signal input bus;
• wherein each of the at least three digital signal input busses includes D digital signal lines, where D is an integer greater than zero;
• wherein the first digital signal input bus and the second digital signal input bus is electrically connected to a first multiplexer, wherein a first control signal selects one of the first and second digital signal input busses to be multiplexed to an output of the first multiplexer, wherein a digital signal output from the first multiplexer is a D-bit wide digital signal that addresses the memory;
• wherein the third digital signal input bus is connected to a second multiplexer controlled by a second control signal, wherein digital input signals connected to the input side of the second multiplexer are test and/or analysis status signals from a plurality of other digital circuit testing and analysis modules;
• and
• wherein the 2D×one-bit wide memory locations are pre-updated with one bit-value indicating a test and/or analysis status of the combination of any D digital signal levels that at any time is applied on the at least one digital input signal bus.

A method of analyzing timing events in a digital circuit, the method comprising:

• providing a plurality of digital circuit testing and analysis modules are connected in a cascade coupling, wherein a first one of the plurality of modules is configured to receive a selected group of digital signals to be tested and analyzed on a digital signal input bus, the digital circuit testing and analysis module including:
• at least one digital signal input bus comprising D digital signal lines, where D is an integer greater than zero and where the D digital signal lines provide a D-bit wide digital stimuli pattern;
• a memory configured to have 2D×one-bit wide memory locations;
• wherein the D-bit wide digital signals are applied as a numerical read-out address of 2D×one-bit wide memory locations of the memory;
• and
• wherein the 2D×one-bit wide memory locations are pre-updated with one bit-value indicating a test and/or analysis status of the combination of any D digital signal levels that at any time is applied on the at least one digital input signal bus;
• configuring a digital signal output bus from a multiplexer controllable by a control signal of the first one of the plurality of testing and analysis modules to be connected to a digital input bus of a second one of the plurality of testing and analysis modules;
• configuring the memory of at least the first one of the plurality of digital testing and analysis modules to detect a first instance of signals levels of the selected group of signals;
• configuring the memory of at least the second one of the plurality of digital testing and analysis modules to detect a second instance of signal levels of the selected group of signals;
• and
• aggregating the test and/or analysis status from at least the first one and from at least the second one of the plurality of testing and analysis modules, wherein each respective one of the testing and analysis modules are associated with different timing events in a test and analysis cycle of the digital circuitry under test and analysis.