Semiconductor memory devices with diode-connected MOS

A method for operating a memory device, comprising:

• providing a plurality of memory cells, each of the plurality of memory cells comprising a first transistor, a second transistor, a third transistor, a diode-connected transistor, and a capacitor, wherein the first, second, third, and diode-connected transistor are coupled in series;
• programming a first one of the plurality of memory cells by performing:
• (i) asserting one of a plurality of word lines (WLs) that is connected to a gate terminal of the first transistor of the first memory cell;
• (ii) asserting one of a plurality of first control lines (CL1) that is connected to a gate terminal of the second transistor of the first memory cell;
• and (iii) applying a programming voltage on one of a plurality of bit lines (BLs) connected to the capacitor of the first memory cell;
• and
• asserting one of a plurality of second control lines (CL2) that is connected to a gate terminal of the third transistor of a second one of the plurality of memory cells, wherein the CL1 also gates the second transistor of the second memory cell and the BL is also connected to the capacitor of the second memory cell.

A memory device, comprising:

• a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a third transistor, a first diode-connected transistor, and a capacitor;
• wherein each of the plurality of non-volatile memory cells is operatively coupled to a word line (WL), a first control line, a second control line, and a bit line (BL);
• wherein the first transistor, second transistor, third transistor, first diode-connected transistor are coupled in series;
• and
• wherein the capacitor has a first terminal connected to a common node between the second transistor and the third transistor, and a second terminal connected to the BL.