Semiconductor storage device
AssigneeSocionext Inc.
InventorTomoyuki Yamada
Life of this patent
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Abstract
A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.
Claims14
A semiconductor storage device provided with a nonvolatile memory cell, comprising:
- first and second word lines extending in a first direction;
- and
- first and second bit lines extending in a second direction perpendicular to the first direction,
- wherein
- the memory cell includes
- a first program transistor having a gate connected to the first word line,
- a first switch transistor, provided between the first program transistor and the first bit line, having a gate connected to the second word line,
- a second program transistor having a gate connected to the first word line, and
- a second switch transistor, provided between the second program transistor and the second bit line, having a gate connected to the second word line,
- the first and second program transistors are three-dimensional transistors of which channel portions overlap each other as viewed in plan,
- the first and second switch transistors are three-dimensional transistors of which channel portions overlap each other as viewed in plan,
- the first program transistor and the first switch transistor are formed in a first layer,
- the second program transistor and the second switch transistor are formed in a second layer located below the first layer, and
- the memory cell includes
- a first local interconnect that is connected to a drain of the first switch transistor and extends from the first switch transistor toward a first-oriented direction in the first direction.
A semiconductor storage device provided with a nonvolatile memory cell, comprising:
- first and second word lines extending in a first direction;
- and
- a first bit line extending in a second direction perpendicular to the first direction,
- wherein
- the memory cell includes
- a first program element having a gate connected to the first word line, and
- a first switch element, provided between the first program element and the first bit line, having a gate connected to the second word line,
- the first program element has first and second program transistors that are three-dimensional transistors connected in parallel of which channel portions overlap each other as viewed in plan, and
- the first switch element includes a first switch transistor that is a three-dimensional transistor formed in a same layer as either one of the first and second program transistors.
Dependencies are inferred from the claim text.