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US 11,688,479 B2Granted
Read window based on program/erase cycles
AssigneeMicron Technology, Inc.
InventorsVamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
Life of this patent
Estimating the term…
Abstract
A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
Claims18
A method, comprising:
- subjecting a group of memory cells of a memory device to a particular quantity of program/erase cycles (PECs) representative of a desired operating characteristic of the memory device and a desired service life of the memory device;
- and
- subsequent to subjecting the group of memory cells to the particular quantity of PECs, assessing a data retention capability of the group of memory cells.
A system, comprising:
- a processing device;
- and
- a memory device couplable to the processing device,
- wherein the processing device is configured to:
- subject a first group of memory cells of the memory device to a plurality of program/erase cycles (PECs), wherein a quantity of the plurality of PECs is based at least in part on a quantity of programming operations undergone by a second group of memory cells of the memory device;
- determine, subsequent to subjection of the first group of memory cells to the plurality of PECs, an operating characteristic of the first group of memory cells;
- and
- adjust a read window for subsequent programming operations performed on the second group of memory cells based on the performance characteristic.
5 more elements
An apparatus, comprising:
- a cyclic buffer portion;
- a snapshot portion comprising:
- a first group of memory cells;
- and
- a second group of memory cells;
- and
- control circuitry coupled to the cyclic buffer portion and the snapshot portion, wherein the control circuitry is configured to:
- subject the first group of memory cells to a plurality of program/erase cycles (PECs) at an accelerated rate relative to a rate of PECs associated with programming the second group of memory cells;
- and
- program the second group of memory cells using an initial target voltage corresponding to a particular data retention capability based on the plurality of PECs.
7 more elements
A system, comprising:
- a processing device;
- and
- a memory device couplable to the processing device and comprising:
- a cyclic buffer portion;
- and
- a snapshot portion comprising:
- a first group of memory cells;
- and
- a second group of memory cells,
- wherein the processing device is configured to:
- subject a first group of memory cells of the memory device to a plurality of program/erase cycles (PECs), wherein a quantity of the plurality of PECs is based at least in part on a quantity of programming operations undergone by a second group of memory cells of the memory device;
- and
- determine, subsequent to subjection of the first group of memory cells to the plurality of PECs, an operating characteristic of the first group of memory cells.
10 more elements
Dependencies are inferred from the claim text.