US 11,688,478 B2 · Nonvolatile memory device with capability of determining degradation of data erase characteristics

Abstract

A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

Claims20

Dependent claims

A nonvolatile memory device comprising:

a memory block including a plurality of memory strings;
and
a control circuit configured to control the memory block,
wherein each memory string includes:
a plurality of memory cells connected in series, stacked in a vertical direction relative to an underlying substrate, and connected to a plurality of wordlines;
two or more ground selection transistors connecting a first end of each memory string to a common source line, and connected to two or more ground selection lines;
and
two or more string selection transistors connecting a second end, opposite the first end, of each memory string to a bitline, and connected to two or more string selection lines, and
wherein the control circuit is configured to perform a data erase operation on the memory block by:
applying an erase voltage having a first erase level higher than a normal erase level to the common source line;
and
applying a gate voltage having a first gate level lower than a normal gate level to one of the two or more ground selection lines.

9 more elements

A nonvolatile memory device comprising:

a memory block including a plurality of memory strings;
and
a control circuit configured to control the memory block,
wherein each memory string includes:
a plurality of memory cells connected in series, stacked in a vertical direction relative to an underlying substrate, and connected to a plurality of wordlines;
two or more ground selection transistors connecting a first end of each memory string to a common source line, and connected to two or more ground selection lines;
and
two or more string selection transistors connecting a second end, opposite the first end, of each memory string to a bitline, and connected to two or more string selection lines, and
wherein the control circuit is configured to perform a data erase operation on the memory block by:
applying an erase voltage having a normal erase level to the common source line;
and
applying a gate voltage having a first gate level lower than a normal gate level to one of the two or more ground selection lines.

9 more elements

A nonvolatile memory device comprising:

a memory block including a plurality of memory strings;
and
a control circuit configured to control the memory block,
wherein each memory string includes:
a plurality of memory cells connected in series, stacked in a vertical direction relative to an underlying substrate, and connected to a plurality of wordlines;
two or more ground selection transistors connecting a first end of each memory string to a common source line, and connected to two or more ground selection lines;
and
two or more string selection transistors connecting a second end, opposite the first end, of each memory string to a bitline, and connected to two or more string selection lines, and
wherein the control circuit is configured to perform a data erase operation on the memory block by:
applying an erase voltage having a first erase level higher than a normal erase level to the common source line;
and
applying a gate voltage having a normal gate level to one of the two or more ground selection lines.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/694,229Filed 14 Mar 2022 · continuation

Priority

KR 10-2018-00634741 Jun 2018

Published

US 2022/0199174 A123 Jun 2022

Granted

27 Jun 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification21 codes

G11C 16/349
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: arrangements for evaluating…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups

Family

Application16/226,810Parent of this continuation-in-part · filed 20 Dec 2018

Application17/021,407Parent of this continuation · filed 15 Sep 2020

US 10,825,530 B2Parent of this continuation-in-part · filed 3 Nov 2020

US 2022/0199174 A1Pre-grant publication · published 23 Jun 2022

US 11,289,170 B2Parent of this continuation

Application17/021,407Parent of this continuation-in-part

US 2019/0371410 A1Published application

US 2020/0411122 A1Published application

US 11,688,478 B2This patent

From the US filing history. Foreign family members aren’t listed.

Nonvolatile memory device with capability of determining degradation of data erase characteristics

Life of this patent

Nonvolatile memory device with capability of determining degradation of data erase characteristics

Life of this patent

Abstract

Claims20