Intra-code word wear leveling techniques

An apparatus, comprising:

• a controller associated with a memory system, wherein the controller is configured to cause the apparatus to:
• execute, at a memory device, a first plurality of access operations over a first duration, wherein to execute the first plurality of access operations, the controller is configured to cause the apparatus to:
• apply a first assignment of logical to physical identifiers for a first subset of the first plurality of access operations associated with addresses that are later in an address order than a value of a pointer;
• and
• apply a second assignment of logical to physical identifiers for a second subset of the first plurality of access operations associated with addresses that are earlier in the address order than the value of the pointer;
• update the value of the pointer based at least in part on a condition being satisfied;
• and
• execute, at the memory device and based at least in part on updating the value of the pointer, a second plurality of access operations over a second duration, wherein to execute the second plurality of access operations, the controller is configured to cause the apparatus to:
• apply the second assignment of logical to physical identifiers for a third subset of the second plurality of access operations associated with addresses that are later in the address order than the updated value of the pointer;
• and
• apply a third assignment of logical to physical identifiers for a fourth subset of the second plurality of access operations associated with addresses that are earlier in the address order than the updated value of the pointer.

A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

• execute, at a memory device, a first plurality of access operations over a first duration, wherein to execute the first plurality of access operations, the instructions are executable by the processor to:
• apply a first assignment of logical to physical identifiers for a first subset of the first plurality of access operations associated with addresses that are later in an address order than a value of a pointer;
• and
• apply a second assignment of logical to physical identifiers for a second subset of the first plurality of access operations associated with addresses that are earlier in the address order than the value of the pointer;
• update the value of the pointer based at least in part on a condition being satisfied;
• and
• execute, at the memory device and based at least in part on updating the value of the pointer, a second plurality of access operations over a second duration, wherein to execute the second plurality of access operations, the instructions are executable by the processor to:
• apply the second assignment of logical to physical identifiers for a third subset of the second plurality of access operations associated with addresses that are later in the address order than the updated value of the pointer;
• and
• apply a third assignment of logical to physical identifiers for a fourth subset of the second plurality of access operations associated with addresses that are earlier in the address order than the updated value of the pointer.