Apparatus and methods for seeding operations concurrently with data line set operations
AssigneeMicron Technology, Inc.
InventorsJun Xu, Yingda Dong
Life of this patent
Estimating the term…
Abstract
A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.
Claims20
A device comprising:
- a common source;
- a three-dimensional array of memory cells comprising a plurality of NAND strings, each NAND string selectively connected between a corresponding data line and the common source;
- a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings;
- and
- a controller configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.
A device comprising:
- a three-dimensional array of memory cells comprising a plurality of NAND strings, each NAND string selectively connected to a corresponding data line, wherein each memory cell of each NAND string is connected to a respective access line of a plurality of access lines;
- and
- a controller to access the three-dimensional array of memory cells, the controller configured to:
- perform a sense operation on a particular memory cell of a selected NAND string of the plurality of NAND strings;
- apply a first voltage level to the respective access line of the plurality of access lines for a second memory cell of the selected NAND string;
- apply a second voltage level higher than the first voltage level to the respective access line of the plurality of access lines for the particular memory cell;
- apply a third voltage level to the data line corresponding the selected NAND string;
- and
- apply a fourth voltage level higher than the third voltage level to the data line corresponding to an unselected NAND string of the plurality of NAND strings.
A device comprising:
- a three-dimensional array of memory cells comprising a plurality of NAND strings;
- and
- a controller to access the three-dimensional array of memory cells, the controller configured to:
- perform a sense operation on a particular memory cell of a selected NAND string of the plurality of NAND strings;
- perform a source-side seeding operation;
- perform a data line set operation;
- and
- apply a programming pulse to the particular memory cell following the source-side seeding operation and the data line set operation.
Dependencies are inferred from the claim text.