Dual verify for quick charge loss reduction in memory cells

A device comprising:

• a page buffer coupled to a bit line of a memory array of memory cells, wherein the page buffer comprises:
• a first transistor path to apply a first voltage on the bit line during a first program verify operation on a first subset of a plurality of the memory cells of the memory array, wherein the first transistor path comprises a first bit line (BL) clamp transistor that is pre-charged to a first gate voltage;
• and
• a second transistor path that is coupled in parallel with the first transistor path, the second transistor path to apply a second voltage, which is higher than the first voltage, to the bit line during a second program verify operation on a second subset of the plurality of the memory cells, wherein the second transistor path comprises a second BL clamp transistor that is pre-charged to a second gate-source voltage that is higher than the first gate voltage by a difference between the second voltage and the first voltage;
• and
• control logic operatively coupled with the page buffer, the control logic to perform operations comprising:
• causing the plurality of the memory cells to be programmed with a first program pulse;
• measuring a threshold voltage for each of the plurality of the memory cells;
• forming a threshold voltage distribution from the measured threshold voltages;
• classifying, based on the threshold voltage distribution, the second subset of the plurality of the memory cells as having a faster quick charge loss than that of the first subset of the plurality of the memory cells;
• and
• triggering on, in response to the classifying, the second transistor path to apply the second voltage to the bit line during the second program verify operation on the second subset of the plurality of the memory cells.

A method of operating a device comprising a page buffer coupled to a bit line of a memory array of memory cells, the page buffer to apply one a first voltage or a second voltage that is higher than the first voltage during a program verify operation performed on the memory cells, and control logic coupled with the page buffer, wherein the method of operating the device comprises:

• causing, by the control logic, a plurality of the memory cells to be programmed with a first program pulse;
• causing, by the control logic, a threshold voltage to be measured at each of the plurality of the memory cells;
• forming, by the control logic, a threshold voltage distribution for the plurality of the memory cells from the measured threshold voltages;
• comparing, using the threshold voltage distribution, a first quick charge loss of a first subset of the plurality of the memory cells to a second quick charge loss of a second subset of the plurality of the memory cells;
• determining, based on the comparing, that the first quick charge loss is faster than the second quick charge loss;
• and
• causing, by the control logic, in response to the determining, the page buffer to apply the second voltage to the bit line during the program verify operation performed on any of the first subset of the plurality of the memory cells until the first subset is programmed beyond the second voltage.