SLC page read

A NAND memory device comprising:

• a first group of pages made up of NAND memory cells that are configured in a first configuration to store a first number of bits in each cell;
• an indicator page of NAND memory cells that stores host data and serves as a read disturb indicator page for the first group of pages, each of the NAND memory cells of the indicator page configured in a second configuration to store a second number of bits in each cell, the first number of bits greater than the second number of bits;
• a memory controller configured to perform operations comprising:
• storing a first host data value in a first of the NAND memory cells of the first group of pages, the first host data value a size of the first number of bits;
• storing a second host data value in a NAND memory cell of the indicator page, the second host data value a size of the second number of bits;
• determining whether a read counter for the first group of pages of NAND memory cells is above a threshold;
• responsive to determining that the read counter is above the threshold, determining whether the indicator page of NAND memory cells indicates a read disturb error;
• and
• responsive to determining that the indicator page of NAND memory cells indicates the read disturb error, scanning pages in the first group of pages to determine whether any of those pages have read-disturb errors.