Reducing programming disturbance in memory devices

A memory structure, comprising:

• a block of vertically-extending memory cell strings, the block including multiple sub-blocks, each memory cell string including a pillar of semiconductor channel material, and extending between a source and a data line, wherein each memory cell in a vertical string is coupled to a respective access line, and wherein access lines connect to memory cells in multiple sub-blocks;
• a memory device controller, comprising control circuitry configured to perform operations on the memory structure, comprising:
• during an initial part of a programming operation, precharging the pillars of multiple memory cell strings in multiple sub-blocks in the block by applying a precharge voltage to the pillars of the memory cell strings;
• and
• during a subsequent part of the programming operation, applying a programming voltage to a selected access line coupled to a selected memory cell in the selected sub-block;
• and
• wherein during the subsequent part of the programing operation, the pillar of at least one unselected memory cell string in an unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on the selected access line.

A memory device, comprising:

• a memory array comprising,
• a block of memory cell strings, comprising,
• multiple strings of NAND memory cells arranged in multiple sub-blocks, the multiple strings of NAND memory cells extending between a source and an associated data line of multiple data lines, each string including,
• multiple NAND memory cells arranged at vertically offset levels along a semiconductor pillar;
• a source select gate between the multiple NAND memory cells and the source;
• a drain select gate between the NAND memory cells and the associated data line;
• and
• multiple access lines coupled to memory cells in a respective level in at least first and second sub-blocks of the multiple sub-blocks;
• a memory device controller, comprising control circuitry configured to perform operations comprising,
• performing a programming operation on a selected memory cell in a selected string of a selected sub-block of the first and second sub-blocks, the programming operation comprising a first portion and a second portion,
• wherein the first portion of the programming operation comprises pre-charging the semiconductor pillars of multiple strings of memory cells in both the selected sub-block and an unselected sub-block with a precharge voltage, including placing the drain select gates of the memory cells strings in a conducting state, and applying a precharge voltage to the data lines in both the selected sub-block and the unselected sub-block;
• wherein the second portion of the programming operation comprises,
• after precharging the semiconductor pillars of the strings of memory cells in the selected sub-block and the unselected sub-block, placing the drain select gates in the unselected sub-block in a non-conducting state;
• maintaining an elevated voltage on data lines not coupled to the selected string containing the selected memory cell;
• and
• applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block of the block of memory cells and to at least one unselected memory cell in the unselected sub-block;
• and
• while applying the programming voltage to the first access line, placing the drain select gate of the selected string in a conductive state.