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US 11,688,469 B2Granted
Non-volatile memory with sub-block based self-boosting scheme
AssigneeSanDisk Technologies LLC
InventorsDengtao Zhao, Gerrit Jan Hemink, Xiang Yang, Ken Oowada, Guirong Liang
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Abstract
To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
Claims19
An apparatus, comprising:
- a control circuit configured to connect to a first NAND string, the first NAND comprising a plurality of non-volatile memory cells connected in series between a source line and a bit line, including a first subset of the memory cells, a second subset of the memory cells connected between the first subset of the memory cells and the source line, and one or more joint transistors connected in series with and in between the first subset and the second subset of the memory cells, the control circuit configured to:
- independently erase either of the first subset of the memory cells and the second subset of the memory cells, where, to erase one but not both of the first subset of the memory cells and the second subset of the memory cells, the control circuit is configured to bias one or more of the joint transistors to be in an off state;
- and
- subsequent to erasing the second subset of the memory cells, but not the first subset of the memory cells, perform a program operation on the first subset of the memory cells, sequentially programming the first subset of the memory cells from memory cells nearer the one or more joint transistors toward memory cells nearer the source line, where, to perform the program operation on the first subset of the memory cells the control circuit is configured to:
- biasing the bit line to one of either a program enable voltage or a program inhibit voltage;
- biasing the memory cells of the first subset to a first pass voltage;
- biasing non-selected memory cells of the second subset to a second pass voltage;
- prior to biasing the non-selected memory cells of the second subset to the second pass voltage, biasing the one or more joint transistors to a voltage level configured to pass the program enable voltage, but not the program inhibit voltage, from first subset of the memory cells to the second subset of the memory cells;
- and
- subsequent to biasing the non-selected memory cells of the second subset to the second pass voltage, applying a programming pulse to a first selected memory cell of the second subset.
7 more elements
A method, comprising:
- erasing a second subset of memory cells, but not a first subset of the memory cells, of a non-volatile memory array, the array comprising a plurality of NAND strings each connected between a corresponding one of a plurality of bit lines and one of one or more source lines, each of the NAND strings comprising the first subset of memory cells each connected to a corresponding one of a first subset of word lines, the second subset of memory cells each connected to a corresponding one of a second subset of word lines and connected between the first subset of the memory cells and the source line, and one or more joint transistors each connect to a corresponding control line and connected in series with and in between the first subset and the second subset of the memory cells;
- subsequent to erasing the second subset of the memory cells, but not the second subset of the memory cells, performing a programing operation on the first subset of the memory cells in which the first subset of the memory cells are sequentially programed from memory cells nearer the one or more joint transistors toward memory cells nearer the source line, comprising:
- biasing each of a plurality of the bit lines to one of plurality of bit line voltage levels, including a program enable voltage and a program inhibit voltage;
- subsequent to biasing the bit lines, performing a channel boosting operation on the plurality of NAND strings by:
- biasing the first subset of word lines to a first pass voltage;
- biasing non-selected word lines of the second subset of word lines to a second pass voltage;
- and
- prior to biasing the non-selected word lines of the second subset of word lines to the second pass voltage, biasing the corresponding control lines of the one or more joint transistors to a voltage level configured to pass the program enable voltage, but not the program inhibit voltage, from the first subset of the memory cells to the second subset of the memory cells;
- and
- applying a programming pulse to a first selected word line of the second subset of word lines subsequent to biasing the non-selected word lines of the second subset of word lines to the second pass voltage.
7 more elements
A non-volatile memory device, comprising:
- an array comprising a plurality of NAND strings each connected between a corresponding one of a plurality of bit lines and one of one or more source lines, each of the NAND strings comprising a first subset of memory cells each connected to a corresponding one of a first subset of word lines, a second subset of memory cells each connected to a corresponding one of a second subset of word lines and connected between the first subset of the memory cells and the source line, and one or more joint transistors each connect to a corresponding control line and connected in series with and in between the first subset and the second subset of the memory cells;
- and
- one or more control circuits connected to the array and configured to
- independently erase either of the first subset of the memory cells and the second subset of the memory cells, where, to erase one but not both of the first subset of the memory cells and the second subset of the memory cells, the control circuit is configured to bias one or more of the joint transistors to be in an off state;
- and
- subsequent to erasing the second subset of the memory cells, but not the second subset of the memory cells, perform a program operation on the first subset of the memory cells, sequentially programming the first subset of the memory cells from memory cells nearer the one or more joint transistors toward memory cells nearer the source line, where, to perform the program operation on the first subset of the memory cells the one or more control circuit are configured to:
- bias each of the bit lines to one of plurality of bit line voltage levels, including a program enable voltage and a program inhibit voltage;
- subsequent to biasing the bit lines, bias the first subset of word lines to a first pass voltage and bias non-selected word lines of the second subset of word lines to a second pass voltage;
- prior to biasing the non-selected word lines of the second subset of word lines to the second pass voltage, bias the corresponding control lines of the one or more joint transistors to a voltage level configured to pass the program enable voltage, but not the program inhibit voltage, from first subset of the memory cells to the second subset of the memory cells;
- and
- subsequent to biasing the non-selected word lines of the second subset of word lines to the second pass voltage, apply a programming pulse to a first selected word line of the second subset of word lines.
8 more elements
Dependencies are inferred from the claim text.