Standby biasing techniques to reduce read disturbs
AssigneeMicron Technology, Inc.
InventorsMichele Piccardi, Xiaojiang Guo, Shigekazu Yamada
Life of this patent
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Abstract
Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
Claims20
A storage system having an active state and a standby state, the storage system comprising:
- a string driver circuit configured to isolate a global word line of a memory device of the storage system from a local word line of the memory device in a first state and to couple the global word line to the local word line in a second state;
- and
- a standby voltage generator circuit configured to provide a high-voltage bias signal to the string driver circuit in an active period of the standby state to enable the string driver circuit to couple the global word line to the local word line in the standby state, wherein the active period of the standby state is shorter than a refresh period of the standby state.
A method comprising:
- isolating, using a string driver circuit, a global word line of a memory device of a storage system from a local word line of the memory device in a first state;
- coupling, using the string driver circuit, the global word line to the local word line in a second state;
- and
- providing, using a standby voltage generator circuit, a high-voltage bias signal to the string driver circuit in an active period of a standby state of the storage system to enable the string driver circuit to couple the global word line to the local word line in the standby state,
- wherein the active period of the standby state is shorter than a refresh period of the standby state.
A storage system having an active state and a standby state, the storage system comprising:
- means for isolating a global word line of a memory device of the storage system from a local word line of the memory device in a first state and coupling the global word line to the local word line in a second state;
- and
- means for providing a high-voltage bias signal to the string driver circuit in an active period of the standby state to enable the string driver circuit to couple the global word line to the local word line in the standby state, wherein the active period of the standby state is shorter than a refresh period of the standby state.
Dependencies are inferred from the claim text.