3D memory device

A three-dimensional (3D) memory device comprising:

• a memory cell array including a plurality of lower memory cells respectively arranged in regions where a plurality of lower word lines intersect with a plurality of bit lines and a plurality of upper memory cells respectively arranged in regions where a plurality of upper word lines intersect with the plurality of bit lines;
• a first row decoder including a plurality of lower row switches respectively connected to a corresponding one of the plurality of lower word lines, the first row decoder performing a selection operation on the plurality of lower word lines;
• a second row decoder including a plurality of upper row switches respectively connected to a corresponding one of the plurality of upper word lines, the second row decoder performing a selection operation on the plurality of upper word lines;
• a first sense amplifier connected to a first lower word line of the plurality of lower word lines, the first sense amplifier configured to perform a data sensing operation on a first lower memory cell connected between a first bit line of the plurality of bit lines and the first lower word line;
• and
• a second sense amplifier connected to a first upper word line of the plurality of upper word lines, the second sense amplifier configured to perform a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line,
• wherein the data sensing operation of the first sense amplifier and the data sensing operation of the second sense amplifier are performed in parallel.