Back to results
US 11,688,460 B2Granted
Memory operation with double-sided asymmetric decoders
AssigneeMicron Technology, Inc.
InventorsFabio Pellizzer, Nevil N. Gajera, John Frederic Schreck
Life of this patent
Estimating the term…
Abstract
As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.
Claims20
A device, comprising:
- a memory array comprising a memory cell configured to be targeted by a current memory operation, wherein the memory cell comprises a phase-change material layer and a select material layer disposed between a wordline and a bitline;
- a first decoder coupled to a first end of the bitline, wherein the first decoder comprises:
- a first delivery driver configured to output a first signal having a first polarity to the bitline;
- and
- a second delivery driver configured to output a second signal having a second polarity to the bitline;
- and
- a control circuit configured to select between activating the first delivery driver and the second delivery driver based at least in part on a previous memory operation associated with the memory cell.
4 more elements
A method for operating a control circuit, comprising:
- determining a characteristic associated with a signal previously delivered to a memory cell;
- transmitting a first control signal to a first delivery driver to turn on a transistor associated with the first delivery driver based at least in part on the characteristic associated with the signal previously delivered to the memory cell;
- and
- transmitting a second control signal to a second delivery driver while the first delivery driver is activated to enable access to the memory cell.
1 more element
A semiconductor device, comprising:
- a memory cell;
- a first decoder comprising a first delivery driver and a second delivery driver, wherein the first delivery driver is configured to generate a first signal having a first polarity, and wherein the second delivery driver is configured to generate a second signal having a second polarity opposite of the first polarity;
- and
- a control circuit configured to:
- receive a first indication associated with a previous memory operation involving the memory cell;
- select the first delivery driver from the first delivery driver and the second delivery driver based at least in part on the first indication;
- and
- in response to selecting the first delivery driver, transmit a control signal to turn on the first delivery driver.
5 more elements
Dependencies are inferred from the claim text.