Gate-all-around memory devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.
Claims20
A memory structure, comprising:
- a first Static Random Access Memory (SRAM) cell comprising
- a first fin-shaped vertical stack over a first p-type well, the first fin-shaped vertical stack comprising a first plurality of nanostructures stacked one over another,
- a second fin-shaped vertical stack over an n-type well adjacent the first p-type well, the second fin-shaped vertical stack comprising a second plurality of nanostructures stacked one over another,
- a third fin-shaped vertical stack over the n-type well, the third fin-shaped vertical stack comprising a third plurality of nanostructures stacked one over another,
- a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well, the fourth fin-shaped vertical stack comprising a fourth plurality of nanostructures stacked one over another,
- a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack,
- a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack, and
- a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack.
A Static Random Access Memory (SRAM) cell, comprising:
- a first fin-shaped vertical stack over a first p-type well, the first fin-shaped vertical stack comprising a first plurality of nanostructures stacked one over another;
- a second fin-shaped vertical stack over an n-type well adjacent the first p-type well, the second fin-shaped vertical stack comprising a second plurality of nanostructures stacked one over another;
- a third fin-shaped vertical stack over the n-type well, the third fin-shaped vertical stack comprising a third plurality of nanostructures stacked one over another;
- a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well, the fourth fin-shaped vertical stack comprising a fourth plurality of nanostructures stacked one over another;
- a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack;
- a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack;
- and
- a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack.
A memory cell, comprising:
- a first vertical stack of nanostructures over a first p-type well;
- a second vertical stack of nanostructure over an n-type well adjacent the first p-type well;
- a third vertical stack of nanostructures over the n-type well;
- a fourth vertical stack of nanostructures over a second p-type well adjacent the n-type well;
- a first dielectric fin between the first vertical stack of nanostructures and the second vertical stack of nanostructures;
- a second dielectric fin between the second vertical stack of nanostructures and the third vertical stack of nanostructures;
- and
- a third dielectric fin between the third vertical stack of nanostructures and the fourth vertical stack of nanostructures.
Dependencies are inferred from the claim text.