Semiconductor memory subword driver circuits and layout
AssigneeMicron Technology, Inc.
InventorKyuseok Lee
Life of this patent
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Abstract
In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.
Claims24
A semiconductor device comprising:
- a first area of a subword driver block, the first area comprising:
- a first active region on which a first transistor and a second transistor are formed, the first active region extending in a first direction, the first and second transistors coupled to different main word lines;
- a second active region on which a third transistor and a fourth transistor are formed, the second active region extending in the first direction;
- a fifth transistor coupled to the first transistor;
- a sixth transistor coupled to the third transistor, the fifth transistor coupled to a first word driver line, the sixth transistor coupled to a second word driver line different from the first word driver line;
- a diffusion region configured to merge the first and second active regions;
- and
- a contact on the first active region between the first transistor and the second transistor in a second direction that is perpendicular to the first direction and coupled to a non-active potential,
- wherein third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.
A semiconductor device comprising:
- a first area of a subword driver block, the first area comprising:
- a first active region extending in a first direction and having a first portion, on which a first transistor and a second transistor are formed, and a second portion, the second portion being narrower than the first portion, the first and second transistors coupled to different main word lines;
- a second active region extending in a first direction and having a third portion, on which a third transistor and a fourth transistor are formed, and a fourth portion, the fourth portion being narrower than the third portion;
- a fifth transistor coupled to the first transistor;
- a sixth transistor coupled to the third transistor, the fifth transistor coupled to a first word driver line, the sixth transistor coupled to a second word driver line different from the first word driver line;
- a diffusion region connecting the first portion and the third portion and configured to merge the first and second active regions;
- and
- a contact on the first active region between the first transistor and the second transistor in a second direction that is perpendicular to the first direction and coupled to a non-active potential,
- wherein third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.
Dependencies are inferred from the claim text.