Semiconductor memory device and memory system including the same

A memory system, comprising:

• a memory device including at least one bank;
• and
• a memory control circuit suitable for:
• dividing the bank into a plurality of sub-regions according to an active address,
• generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions,
• generating a row hammer address according to the aging signal, and
• providing the aging signal, and a target refresh command with the row hammer address,
• wherein the memory device is suitable for performing a target refresh operation on a word line corresponding to the row hammer address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal.

A memory controller, comprising:

• a processor suitable for generating an active command and an active address corresponding to a request from a host;
• a sub-counting circuit suitable for:
• dividing at least one bank of a memory device into a plurality of sub-regions according to the active address, and
• generating a plurality of counting values by counting a number of inputs of the active command for each of the sub-regions based on the active address;
• an aging decision circuit suitable for generating an aging signal for the bank and a count reset signal by calculating an average of the counting values and calculating a standard deviation based on the average, wherein the count reset signal initializes the sub-counting circuit;
• and
• a tracking circuit suitable for:
• generating a target refresh command based on the active command, and
• generating a row hammer address corresponding to the active address according to the aging signal and the counting values when the number of inputs of the active command for the bank is greater than a preset number.