Memory cell, memory cell arrangement, and methods thereof

A memory cell arrangement, comprising:

• a plurality of memory cells, and
• a set of word-lines;
• a set of bit-nodes, a set of lever-lines, and a set of source-nodes configured to address the plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises:
• a field-effect transistor structure having a source region and a drain region,
• a first capacitor structure electrically conductively connected to a corresponding word-line of the set of word-lines and to a gate region of the field-effect transistor structure, and
• a second capacitor structure electrically conductively connected to a corresponding lever-line of the set of lever-lines and to the gate region of the field-effect transistor structure;
• and
• wherein memory cells of a respective subset of the plurality of memory cells share a corresponding word-line of the set of word-lines and are configured to provide a series connection between a corresponding source-node of the set of source-nodes and a corresponding bit-node of the set of bit-nodes via source regions and drain regions of the memory cells of the respective subset.

A method for operating a memory cell, the method comprising:

• reading the memory cell, wherein reading the memory cell comprises:
• applying a read voltage via a word-line to a first control node of a memory cell, a word-line node being connected to a memory element of the memory cell, and applying a first lever voltage via a lever-line to a lever-node of the memory cell, the lever node being connected to a lever-capacitor of the memory cell;
• and
• writing the memory cell, wherein writing the memory cell comprises:
• applying a write voltage to the word-line node of the memory cell, and applying a second lever voltage different from the first lever voltage to the lever-line node of the memory cell.