Wordline driver architecture

A device comprising:

• first circuitry having wordline drivers coupled to wordlines;
• and
• second circuitry having switch structures that are coupled between a first voltage and ground, wherein the switch structures are configured to provide a second voltage to a power connection of each wordline driver based on the first voltage,
• wherein the first circuitry refers to driver circuitry,
• wherein the wordlines include a first wordline and a second wordline, and
• wherein the wordline drivers include a first wordline driver coupled to the first wordline and a second wordline driver coupled to the second wordline.

A device comprising:

• first circuitry having wordline drivers coupled to wordlines;
• and
• second circuitry having switch structures that are coupled between a first voltage and ground, wherein the switch structures are configured to provide a second voltage to a power connection of each wordline driver based on the first voltage,
• wherein the second circuitry refers to header-clamp circuitry,
• wherein the switch structures include a first P-type transistor and a second P-type transistor,
• wherein the first P-type transistor is coupled between the first voltage and the second P-type transistor so as to operate as a header, and
• wherein the second P-type transistor is coupled between the first P-type transistor and ground so as to operate as a clamp.

A device comprising:

• header circuitry coupled to a power distribution line, wherein the header circuitry has a first set of transistors coupled between a source voltage and ground, wherein the first set of transistors are configured to provide a first internal voltage to the power distribution line based on the source voltage;
• and
• row driver circuitry coupled to the power distribution line, wherein the row driver circuitry has a second set of transistors coupled between the source voltage and ground, wherein the second set of transistors are configured to provide a second internal voltage to the power distribution line based on the source voltage,
• wherein the row driver circuitry has wordline drivers coupled to bitcells in an array of bitcells with wordlines, and wherein the wordlines include a first wordline and a second wordline, and wherein the wordline drivers include a first wordline driver coupled to the first wordline and a second wordline driver coupled to the second wordline.

A device comprising:

• header circuitry coupled to a power distribution line, wherein the header circuitry has a first set of transistors coupled between a source voltage and ground, wherein the first set of transistors are configured to provide a first internal voltage to the power distribution line based on the source voltage;
• row driver circuitry coupled to the power distribution line, wherein the row driver circuitry has a second set of transistors coupled between the source voltage and ground, wherein the second set of transistors are configured to provide a second internal voltage to the power distribution line based on the source voltage;
• and
• memory circuitry having an array of bitcells,
• wherein the row driver circuitry has wordline drivers coupled to bitcells in the array of bitcells with wordlines,
• wherein the second set of transistors are configured to provide the second internal voltage to a power connection of each wordline driver based on the source voltage,
• wherein the wordlines include a first wordline and a second wordline, and
• wherein the wordline drivers include a first wordline driver coupled to the first wordline and a second wordline driver coupled to the second wordline.

A device comprising:

• header circuitry coupled to a power distribution line, wherein the header circuitry has a first set of transistors coupled between a source voltage and ground, wherein the first set of transistors are configured to provide a first internal voltage to the power distribution line based on the source voltage;
• and
• row driver circuitry coupled to the power distribution line, wherein the row driver circuitry has a second set of transistors coupled between the source voltage and ground, wherein the second set of transistors are configured to provide a second internal voltage to the power distribution line based on the source voltage,
• wherein the header circuitry refers to first header circuitry and second header circuitry,
• wherein the second header circuitry is coupled to the power distribution line,
• wherein the second header circuitry has a third set of transistors coupled between the source voltage and ground, and
• wherein the third set of transistors are configured to provide a third internal voltage to the power distribution line based on the source voltage.

A method comprising:

• coupling wordline drivers to wordlines;
• coupling a header transistor between a source voltage and an internal node;
• coupling a clamp transistor to the header transistor at the internal node, wherein the clamp transistor is coupled between the header transistor and ground;
• routing buried conductive lines between the internal node and power connections of the wordline drivers;
• and
• activating the header transistor while deactivating the clamp transistor so as to provide an internal voltage from the internal node to the power connections of the wordline drivers by way of the buried conductive lines based on the source voltage.