US 11,688,443 B2Granted

Semiconductor device

AssigneeSK hynix Inc.

InventorDong Uk Lee

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes: a first transfer path outputting a first preliminary signal; a second transfer path outputting a second preliminary signal; a third transfer path outputting a third preliminary signal; a first calibration circuit generating a first calibration code corresponding to a difference in delay values between the first transfer path and a selected transfer path having a largest delay value among the first to third transfer paths; a second calibration circuit generating a second calibration code corresponding to a difference in delay values between the second transfer path and the selected transfer path; a third calibration circuit generating a third calibration code corresponding to a difference in delay values between the third transfer path and the selected transfer path; a first delay control circuit generating a first signal; a second delay control circuit generating a second signal; and a third delay control circuit generating a third signal.

Claims17

Dependent claims

A semiconductor device, comprising:

a first transfer path suitable for receiving a source signal and outputting a first preliminary signal;
a second transfer path suitable for receiving the source signal and outputting a second preliminary signal;
a third transfer path suitable for receiving the source signal and outputting a third preliminary signal;
a first calibration circuit suitable for generating a first calibration code corresponding to a difference in delay values between the first transfer path and a selected transfer path having a largest delay value among the first to third transfer paths;
a second calibration circuit suitable for generating a second calibration code corresponding to a difference in delay values between the second transfer path and the selected transfer path;
a third calibration circuit suitable for generating a third calibration code corresponding to a difference in delay values between the third transfer path and the selected transfer path;
a first delay control circuit suitable for generating a first signal by delaying the first preliminary signal with a delay value which is determined based on the first calibration code;
a second delay control circuit suitable for generating a second signal by delaying the second preliminary signal with a delay value which is determined based on the second calibration code;
and
a third delay control circuit suitable for generating a third signal by delaying the third preliminary signal with a delay value which is determined based on the third calibration code.

7 more elements

A semiconductor device comprising a plurality of stacked chips, to which different chip identifiers (IDs) are set, each chip including:

a transfer path suitable for transferring a source signal, which is transferred through a first normal through-electrode, and outputting a preliminary signal;
a delay control circuit suitable for generating an internal strobe signal by delaying the preliminary signal with a delay value which is determined based on a calibration code;
a replica circuit suitable for simulating a delay value of the transfer path and generating a test signal by delaying a test source signal which is transferred through a first test through-electrode;
a driving circuit suitable for transferring the generated test signal to a second test through-electrode corresponding to a chip ID among second test through-electrodes;
and
a calibration circuit suitable for generating the calibration code based on the generated test signal and test signals transferred from the other chips through the second test through-electrodes.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/569,222Filed 5 Jan 2022
Priority: KR 10-2021-012093410 Sep 2021
Published: US 2023/0082703 A116 Mar 2023
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/24
Address generation devices; Devices for accessing memories, e.g. details of addressing circuits: accessing extra cells, e.g. dummy cells or…