Back to results
US 11,688,442 B2Granted
Clock signal processing circuit, semiconductor apparatus, and semiconductor system
AssigneeSK hynix Inc.
InventorGi Moon Hong
Life of this patent
Estimating the term…
Abstract
A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.
Claims22
A clock signal processing circuit comprising:
- a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.
A semiconductor apparatus comprising:
- a training circuit configured to perform a clock training operation only once in an initial power-up process and configured to refrain from performing the clock training operation with respect to a self-refresh exit command and a clock training entry command after the initial power-up process;
- and
- a clock signal processing circuit configured to perform a clock buffer control operation that controls an output of a clock buffer, which receives a data clock signal, according to at least one of the self-refresh exit command and the clock training entry command.
A semiconductor system comprising:
- a semiconductor apparatus configured to perform a clock training operation only once in an initial power-up process, and perform a clock buffer control operation that controls an output of a clock buffer that is configured to receive a data clock signal according to at least one of a self-refresh exit command and a clock training entry command, other than performing the clock training operation with respect to the self-refresh exit command and the clock training entry command after the initial power-up process;
- and
- a controller configured to provide at least one of a system clock signal, the data clock signal, the self-refresh exit command, and the clock training entry command to the semiconductor apparatus and provide the data clock signal with different frequencies in a preliminary section and a main section to the semiconductor apparatus, wherein the controller provides the data clock signal with a lower frequency in the preliminary section than a target frequency of the main section.
Dependencies are inferred from the claim text.