On-die termination of address and command signals

A memory device comprising:

• a set of inputs, including first inputs to receive command/address (CA) signals, a second input to receive a chip select (CS) signal, and third inputs to receive a clock (CK) signal;
• a first register comprising a plurality of register fields, wherein:
• a first group of register fields are configured to store values for selecting one of a plurality of CS on-die termination (ODT) impedance values for application to the second input that receives the CS signal;
• and
• a second group of register fields are configured to store values for selecting one of a plurality of CK ODT impedance values for application to the third inputs that receive the CK signal;
• and
• a second register comprising a plurality of register fields configured to store values for selecting one of a plurality of CA ODT impedance values for application to the first inputs that receive the CA signals.

A method of operating a memory device, the method comprising:

• receiving command/address (CA) signals, a chip select (CS) signal, and a clock (CK) signal, at a plurality of inputs;
• storing values in a first register of the memory device, including
• storing in a first register field of the first register, a value for enabling application of one of a plurality of CA on-die termination (ODT) impedance values to the inputs that receive the CA signals;
• storing in a second register field of the first register, a value for enabling application of one of a plurality of CS ODT impedance values to the input that receives the CS signal;
• and
• storing in a third register field of the first register, a value for enabling application of a CK ODT impedance value to the inputs that receive the CK signal;
• storing in a second register of the memory device, a value for selecting a CA ODT impedance value of the plurality of CA ODT impedance values;
• storing in a third register of the memory device, a value for selecting a CS ODT impedance value of the plurality of CS ODT impedance values;
• and
• applying termination impedances to the plurality of inputs that receive the CA signals and CS signal respectively in accordance with the values stored in the second register and third register.