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US 11,688,439 B2Granted
Integrated circuit having data output circuit and semiconductor memory system including the same
AssigneeSK hynix Inc.
InventorDong Heon Lee
Life of this patent
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Abstract
An integrated circuit includes a drivability control circuit and a data output circuit. The drivability control circuit is configured to generate a drivability control signal based on data patterns of a plurality of pieces of data. The data output circuit is configured to control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.
Claims18
An integrated circuit comprising:
- a drivability control circuit configured to input a plurality of pieces of data through a data input terminal and generate a drivability control signal corresponding to each of the plurality of pieces of data based on data patterns of the plurality of pieces of data;
- and
- a data output circuit configured to input the plurality of pieces of data through the data input terminal, input an internal clock signal and output the plurality of pieces of data sequentially through an data output terminal based on the internal clock signal and control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.
A semiconductor memory system comprising:
- a host apparatus configured to output step setting information;
- and
- a semiconductor memory apparatus coupled to the host including:
- a drivability control circuit configured to input a plurality of pieces of data through a data input terminal, input the step setting information and generate a drivability control signal corresponding to each of the plurality of pieces of data based on data patterns of the plurality of pieces of data, wherein a drivability control step of the semiconductor memory apparatus is set based on the step setting information;
- and
- a data output circuit configured to input the plurality of pieces of data through the data input terminal, input an internal clock signal and output the plurality of pieces of data sequentially through an data output terminal based on the internal clock signal and control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.
3 more elements
Dependencies are inferred from the claim text.