Internal voltage generation circuit and semiconductor memory apparatus including the same

A semiconductor memory apparatus comprising:

• a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage which is fed back to the voltage comparison circuit;
• a voltage driving circuit configured to generate an internal voltage in response to the control voltage, the internal voltage being used to generate the feedback voltage;
• a drivability control circuit directly connected to a node, from which the control voltage is outputted, and configured to be turned on in response to an activation of an enable signal which is activated during an active operation and pull-down a voltage level of the control voltage in response to the activation of the enable signal;
• and
• a loading control circuit connected in series with the drivability control circuit, and configured to adjust a resistance value reflected into the drivability control circuit in response to data information inputted to or outputted from a memory cell array circuit which is driven by the internal voltage, the data information inputted to a gate of the loading control circuit.

A semiconductor memory apparatus comprising:

• a memory cell array configured to store data;
• and
• an internal voltage generation circuit including:
• a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage with a feedback voltage;
• a voltage driving circuit configured to generate an internal voltage in response to the control voltage and provide the internal voltage to the memory cell array, the internal voltage being fed back to the voltage comparison circuit as the feedback voltage;
• a drivability control circuit directly connected to a node, from which the control voltage is outputted, and configured to adjust a voltage level of the control voltage to control drivability of the voltage driving circuit in response to at least one of process, voltage, temperature (PVT) skew and values in the data;
• a loading control circuit configured to adjust a resistance value reflected into the drivability control circuit in response to data information inputted to or outputted from the memory cell array which is driven by the internal voltage;
• and
• a data counting circuit configured to generate the data information by counting the number of times that the value of previous data stored in the memory cell array is different from the value of current data inputted to the memory cell array.