Driving method of a pixel circuit, display panel, and display device

A driving method for a pixel circuit,

• the pixel circuit comprising at least one driving transistor, at least one data-writing transistor, at least one compensating transistor, a first initializing transistor, a second initializing transistor, a third initializing transistor, and at least one light-emitting element, wherein:
• the compensating transistor is connected between a gate of the driving transistor and a second pole of the driving transistor,
• the second pole of the driving transistor is connected to an initialization power supply through the first initializing transistor,
• the data-writing transistor is connected between a data voltage input terminal and a first pole of the driving transistor,
• the second initializing transistor is connected between a first power voltage input terminal and the first pole of the driving transistor,
• the lighting element is connected between the second pole of the driving transistor and a second power voltage input terminal,
• the third initializing transistor is connected between the initialization power supply and a first pole of the light emitting element, and
• a gate of the first initializing transistor is connected to a gate of the third initializing transistor;
• the driving method comprises:
• in an initialization stage:
• providing turn-on control signals for a gate of the first initializing transistor, the gates of the second and third initializing transistors, and a gate of the compensating transistor,
• providing a fixed voltage for the first power voltage input terminal;
• and
• in a data-writing stage, providing a turn-on control signal for a gate of the data-writing transistor.

A display panel comprising a pixel circuit, the pixel circuit comprising:

• at least one driving transistor, at least one data-writing transistor, at least one compensating transistor, a first initializing transistor, a second initializing transistor, a first light-emitting control transistor, and a second light-emitting control transistor, wherein:
• the compensating transistor is connected between a gate of the driving transistor and a second pole of the driving transistor,
• the second pole of the driving transistor is connected to an initialization power supply through the first initializing transistor,
• the data-writing transistor is connected between a data voltage input terminal and a first pole of the driving transistor,
• the second initializing transistor is connected between the first pole of the driving transistor and a gate of the second light-emitting control transistor,
• the second pole of the driving transistor is connected to a first pole of a light-emitting element through the second light-emitting control transistor,
• a second pole of the light-emitting element is connected to a second power voltage input terminal such that the second pole of the driving transistor is connectable to the second power voltage input terminal through the light-emitting element and the second light-emitting control transistor, and
• the first pole of the driving transistor is connected to a first power voltage input terminal through the first light-emitting control transistor;
• wherein the pixel circuit further comprises a first scanning line, a second scanning line, a third scanning line, a fourth scanning line, a data line, a gate driver and a data driver;
• wherein the first scanning line is electrically connected to gates of the first and second initializing transistors of the pixel circuit, the second scanning line is electrically connected to a gate of the compensating transistor, the third scanning line is electrically connected to a gate of the first light-emitting control transistor, the fourth scanning line is electrically connected to a gate of the data-writing transistor, and the data line is electrically connected to the data voltage input terminal;
• wherein the first scanning line, the second scanning line, the third scanning line and the fourth scanning line are electrically connected to output terminals of the gate driver in a one to one correspondence, and the data line is electrically connected to an output terminal of the data driver;
• the gate driver is configured to provide a first pulse signal for the first scanning line, the second scanning line and the third scanning line in an initialization stage, and the gate driver is configured to provide a first pulse signal for the fourth scanning line in a data-writing stage;
• and
• the data driver is configured to provide a data voltage for the data line in the data-writing stage.